公开(公告)号：US11257948B2

公开(公告)日：2022-02-22

申请号：US16563366

申请日：2019-09-06

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/74 ,  H01L21/762 ,  H01L21/765

Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

公开(公告)号：US11527617B2

公开(公告)日：2022-12-13

申请号：US17201021

申请日：2021-03-15

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

公开(公告)号：US20220037468A1

公开(公告)日：2022-02-03

申请号：US17201021

申请日：2021-03-15

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

公开(公告)号：US12211807B2

公开(公告)日：2025-01-28

申请号：US18490866

申请日：2023-10-20

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

IPC: H01L23/64 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

公开(公告)号：US11830830B2

公开(公告)日：2023-11-28

申请号：US17318556

申请日：2021-05-12

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

IPC: H01L23/64 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/647 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2223/6672

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

公开(公告)号：US20240047387A1

公开(公告)日：2024-02-08

申请号：US18490866

申请日：2023-10-20

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

IPC: H01L23/64 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/647 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2223/6672

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

公开(公告)号：US20220367388A1

公开(公告)日：2022-11-17

申请号：US17318556

申请日：2021-05-12

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Sheldon Douglas Haynie ,  Ujwal Radhakrishna

IPC: H01L23/64 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.

公开(公告)号：US20200274002A1

公开(公告)日：2020-08-27

申请号：US16281626

申请日：2019-02-21

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie

IPC: H01L29/808 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: An IC with a split-gate transistor includes a substrate doped the second conductivity type having a semiconductor surface layer doped the first conductivity type. The transistor includes a first doped region formed as an annulus, a second doped region including under the first doped region, and a third doped region under the second doped region, all coupled together and doped the second conductivity type. A fourth doped region doped the first conductivity type is above the third doped region. A fifth doped region doped the first conductivity type is outside the annulus. Sixth doped regions doped the first conductivity type include a first sixth doped region surrounded by the annulus in the semiconductor surface layer and a second sixth doped region in the fifth doped region. Field oxide includes a field oxide portion between the fifth and the first doped region. A field plate is on the field oxide portion.

公开(公告)号：US20250140560A1

公开(公告)日：2025-05-01

申请号：US18496697

申请日：2023-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jackson Bauer ,  Sheldon Douglas Haynie ,  John Arch ,  Asad Haider

IPC: H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit (IC) device including one or more corrugated channel structures formed in a top portion of a semiconductor substrate, where a corrugated channel structure includes a first sidewall, a second sidewall and an upper portion. In an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.

公开(公告)号：US20230411452A1

公开(公告)日：2023-12-21

申请号：US17829009

申请日：2022-05-31

Applicant: Texas Instruments Incorporated

Inventor： Sheldon Douglas Haynie ,  Alexei Sadovnikov ,  Brian Goodlin

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0657 ,  H01L29/66795 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7853

Abstract: A method forms a semiconductor device with a substrate including semiconductor material formed to include plural corrugation members, each member including a top surface, and a first and second sidewall extending from the top surface to a lower surface. The method forms a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume and a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume. Both source and drain are formed by initially diffusing a dopant in a uniform manner normal to various portions, some non-coplanar, of the source and drain, respectively.