CHARGE PUMP RECTIFIER
    1.
    发明申请

    公开(公告)号:US20250047199A1

    公开(公告)日:2025-02-06

    申请号:US18362040

    申请日:2023-07-31

    Abstract: A circuit includes a charge pump stage and a common-mode filter. The charge pump stage includes first and second transistors, and first and second capacitors. The second transistor has a first terminal coupled to a control terminal of the first transistor, has a second terminal, and has a control terminal coupled to a first terminal of the first transistor. The first capacitor is coupled between a second terminal of the first transistor and the control terminal of the first transistor. The second capacitor is coupled between the second terminal of the second transistor and the control terminal of the second transistor. The common-mode filter includes third and fourth capacitors. The third capacitor is coupled between the second terminal of the first transistor and the control terminal of the first transistor. The fourth capacitor is coupled between the third capacitor and the control terminal of the second transistor.

    OPTO-EMULATOR
    2.
    发明申请

    公开(公告)号:US20250076348A1

    公开(公告)日:2025-03-06

    申请号:US18524737

    申请日:2023-11-30

    Abstract: An opto-emulator transmitter includes: a current controller; an oscillator circuit; and receiver replica circuitry. The current controller has a first terminal, a second terminal, and a third terminal. The oscillator circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the oscillator circuit is coupled to the second terminal of the current controller. The receiver replica circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the receiver replica circuitry is coupled to the second terminal of the oscillator circuit. The second terminal of the receiver replica circuitry is coupled to the third terminal of the oscillator circuit. The third terminal of the receiver replica circuitry is coupled to the third terminal of the current controller.

    INTEGRATED CIRCUIT WITH BONDWIRE FAULT DETECTION CIRUIT

    公开(公告)号:US20240195412A1

    公开(公告)日:2024-06-13

    申请号:US18194289

    申请日:2023-03-31

    CPC classification number: H03K17/6874

    Abstract: A circuit includes a switch and a switch controller. The switch has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a ground terminal and to a first bondwire terminal. The switch controller includes: a first resistor, a second resistor, a capacitor, and a buffer circuit. The first resistor has a first terminal coupled to a second bondwire terminal. The second resistor has a first terminal coupled to the voltage supply terminal and has a second terminal coupled to a second terminal of the first resistor. The capacitor has a first terminal coupled to the ground terminal and to the first bondwire terminal and has a second terminal coupled to second terminals of the first and second resistors. The buffer circuit has a terminal coupled to the second terminal of the capacitor and has an output terminal coupled to the control terminal of the switch.

    FAST DISCHARGE CIRCUIT
    5.
    发明公开

    公开(公告)号:US20240195409A1

    公开(公告)日:2024-06-13

    申请号:US18194267

    申请日:2023-03-31

    CPC classification number: H03K17/6871

    Abstract: A circuit incudes: a first transistor; a capacitor; a second transistor; and a second resistor. The first transistor has a current terminal and a first control terminal. The capacitor has a capacitor terminal coupled to the current terminal of the first transistor. The second transistor has a first current terminal, a second current terminal, and a second control terminal. The first current terminal of the second transistor is coupled to the capacitor terminal. The second current terminal of the second transistor is coupled to the first control terminal. The resistor has a resistor terminal coupled to the second control terminal.

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