公开(公告)号：US11604221B1

公开(公告)日：2023-03-14

申请号：US17566190

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Sriraj Chellappan ,  Shruti Gupta

IPC: G01R31/317 ,  G01R31/3177 ,  G11C19/28 ,  H03K19/20

Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

公开(公告)号：US12216160B2

公开(公告)日：2025-02-04

申请号：US18182848

申请日：2023-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Sriraj Chellappan ,  Shruti Gupta

IPC: G01R31/317 ,  G01R31/3177 ,  G11C19/28 ,  H03K19/20

Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

公开(公告)号：US20240201997A1

公开(公告)日：2024-06-20

申请号：US18068030

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Kedar Chitnis ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Donald Steiss ,  Mohammad Asif Farooqui ,  Nikhil Sangani ,  Sriraj Chellappan

IPC: G06F9/345 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/345 ,  G06F9/30021 ,  G06F9/3877 ,  G06F9/5016 ,  G06F9/5027

Abstract: Various embodiments disclosed herein relate to compute offloading by supplying operands to hardware accelerators from central processing units. An example embodiment includes a system configured to perform compute offloading. The system comprises a processing unit configured to write data to a memory and a memory adaptor bridge coupled between the processing unit and the memory. The memory adaptor bridge is configured to, in response to an attempt by the processing unit to write an operand to a memory location mapped to a function of a hardware accelerator, write the operand to a different memory location accessible by the hardware accelerator. The memory adaptor bridge is further configured to obtain a result of the function performed on the operand by the hardware accelerator and provide the result of the function to a memory location accessible by the processing unit.

公开(公告)号：US20230243887A1

公开(公告)日：2023-08-03

申请号：US18182848

申请日：2023-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Sriraj Chellappan ,  Shruti Gupta

IPC: G01R31/317 ,  H03K19/20 ,  G11C19/28 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  H03K19/20 ,  G11C19/287 ,  G01R31/3177

Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.