公开(公告)号：US12067244B2

公开(公告)日：2024-08-20

申请号：US18060457

申请日：2022-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Mel Alan Phipps ,  Prasad Jondhale ,  Mohd Asif Farooqui ,  Shailesh Ghotgalkar

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.

公开(公告)号：US12125122B2

公开(公告)日：2024-10-22

申请号：US17556161

申请日：2021-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Ankur Ankur ,  Mayank Mangla ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06T1/20 ,  G06F9/48 ,  G06F11/10 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4812 ,  G06F11/1004 ,  G06T1/60

Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.

公开(公告)号：US12111780B2

公开(公告)日：2024-10-08

申请号：US17677638

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Ankur Ankur ,  Vivek Vilas Dhande ,  Kedar Satish Chitnis ,  Niraj Nandan ,  Brijesh Jadav ,  Shyam Jagannathan ,  Prithvi Shankar Yeyyadi Anantha ,  Santhanakrishnan Narayanan Narayanan

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4221 ,  G06F15/7807

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

公开(公告)号：US20240370170A1

公开(公告)日：2024-11-07

申请号：US18770866

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Mel Alan Phipps ,  Prasad Jondhale ,  Mohd Asif Farooqui ,  Shailesh Ghotgalkar

IPC: G06F3/06

Abstract: Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.

公开(公告)号：US11940909B2

公开(公告)日：2024-03-26

申请号：US17729252

申请日：2022-04-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.

公开(公告)号：US20230333858A1

公开(公告)日：2023-10-19

申请号：US17721534

申请日：2022-04-15

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  H04L9/32

CPC classification number: G06F9/4401 ,  H04L9/3247

Abstract: An example apparatus includes: a first interface configured to couple to a processor core; a second interface configured to couple to a first memory configured to store an image that includes a set of slices; a third interface coupled to the first interface, the third interface configured to couple to a second memory; a direct memory access circuit coupled to the second interface and the third interface and configured to: receive a transaction from the second interface, wherein the transaction specifies a read of a slice of the set of slices; and based on the transaction: read the slice from the first memory; perform on-the-fly operations to the slice; and store the slice in the second memory.

公开(公告)号：US12210449B2

公开(公告)日：2025-01-28

申请号：US18426053

申请日：2024-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06F12/02

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in the faster access memory, which is associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use. The technique is flexible for different memory hierarchies.

公开(公告)号：US20240201997A1

公开(公告)日：2024-06-20

申请号：US18068030

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Kedar Chitnis ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Donald Steiss ,  Mohammad Asif Farooqui ,  Nikhil Sangani ,  Sriraj Chellappan

IPC: G06F9/345 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/345 ,  G06F9/30021 ,  G06F9/3877 ,  G06F9/5016 ,  G06F9/5027

Abstract: Various embodiments disclosed herein relate to compute offloading by supplying operands to hardware accelerators from central processing units. An example embodiment includes a system configured to perform compute offloading. The system comprises a processing unit configured to write data to a memory and a memory adaptor bridge coupled between the processing unit and the memory. The memory adaptor bridge is configured to, in response to an attempt by the processing unit to write an operand to a memory location mapped to a function of a hardware accelerator, write the operand to a different memory location accessible by the hardware accelerator. The memory adaptor bridge is further configured to obtain a result of the function performed on the operand by the hardware accelerator and provide the result of the function to a memory location accessible by the processing unit.

公开(公告)号：US11710030B2

公开(公告)日：2023-07-25

申请号：US16556733

申请日：2019-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06N3/063 ,  G06N3/04 ,  G06F15/78 ,  G06F11/10 ,  G06F17/16 ,  G06N3/048

CPC classification number: G06N3/063 ,  G06F11/1004 ,  G06F15/7807 ,  G06F17/16 ,  G06N3/048

Abstract: A hardware neural network engine which uses checksums of the matrices used to perform the neural network computations. For fault correction, expected checksums are compared with checksums computed from the matrix developed from the matrix operation. The expected checksums are developed from the prior stage of the matrix operations or from the prior stage of the matrix operations combined with the input matrices to a matrix operation. This use of checksums allows reading of the matrices from memory, the dot product of the matrices and the accumulation of the matrices to be fault corrected without triplication of the matrix operation hardware and extensive use of error correcting codes. The nonlinear stage of the neural network computation is done using triplicated nonlinear computational logic. Fault detection is done in a similar manner, with fewer checksums needed and correction logic removed as compared to the fault correction operation.

公开(公告)号：US20230076376A1

公开(公告)日：2023-03-09

申请号：US17470528

申请日：2021-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robin O. Hoel ,  Eric Peeters ,  Prithvi Shankar Yeyyadi Anantha ,  Aniruddha Periyapatna Nagendra ,  Shobhit Singhal ,  Ruchi Shankar ,  Prachi Mishra

IPC: H04L29/06 ,  G06F13/36

Abstract: A microcontroller is provided and comprises a central repository, a processing device, and a firewall. Rule repository memory in the central repository stores one or more access rules defining an access permission of a software context to one or more target resources of the microcontroller. The firewall receives a bus transaction initiated based on an instruction and determines whether any access rule stored in memory of the firewall defines the access permission of the software context to a destination resource. If no access rule stored in the firewall memory defines the access permission, the firewall communicates a miss query condition to the central repository. The central repository searches the rule repository memory for an access rule defining the access permission of the software context to the destination resource, and if a related access rule is found, the related access rule is stored in the firewall memory.