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    Frequency Scaled Segmented Scan Chain for Integrated Circuits
    4.
    发明申请
    Frequency Scaled Segmented Scan Chain for Integrated Circuits 有权
    用于集成电路的频率分段扫描链

    公开(公告)号：US20160266202A1

    公开(公告)日：2016-09-15

    申请号：US14985699

    申请日：2015-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Rajesh Kumar Mittal ,  Wilson Pradeep ,  Vivek Singhal

    IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/28

    CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31725 ,  G01R31/318538 ,  G01R31/318563 ,  G01R31/318575

    Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

    Abstract translation: 扫描链可以形成在整个集成电路中，其中扫描链包括至少第一段和第二段。 通过以奇数时钟对第一段中的多个扫描单元的其余部分进行计时，同时以奇数时钟计时第一段的第一扫描单元，将测试图案的第一部分扫描到第一段中，其中奇数 时钟与偶数时钟异相，其中偶数时钟和奇数时钟具有等于测试图案的扫描速率除以整数N的速率。测试图案的第二部分被扫描到第二段中 以奇数时钟对第二段中的多个扫描单元进行计时，使得测试图案的第二部分不被扫描到第一段中。

    CLOCK SHAPER CIRCUIT FOR TRANSITION FAULT TESTING
    5.
    发明公开
    CLOCK SHAPER CIRCUIT FOR TRANSITION FAULT TESTING 审中-公开

    公开(公告)号：US20230243887A1

    公开(公告)日：2023-08-03

    申请号：US18182848

    申请日：2023-03-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Wilson Pradeep ,  Sriraj Chellappan ,  Shruti Gupta

    IPC: G01R31/317 ,  H03K19/20 ,  G11C19/28 ,  G01R31/3177

    CPC classification number: G01R31/31727 ,  H03K19/20 ,  G11C19/287 ,  G01R31/3177

    Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

    Phase controlled codec block scan of a partitioned circuit device
    6.
    发明授权
    Phase controlled codec block scan of a partitioned circuit device 有权

    公开(公告)号：US11519964B2

    公开(公告)日：2022-12-06

    申请号：US17353882

    申请日：2021-06-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Prakash Narayanan ,  Wilson Pradeep

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

    Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

    Phase controlled codec block scan of a partitioned circuit device
    8.
    发明授权
    Phase controlled codec block scan of a partitioned circuit device 有权

    公开(公告)号：US11073557B2

    公开(公告)日：2021-07-27

    申请号：US16406858

    申请日：2019-05-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Prakash Narayanan ,  Wilson Pradeep

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

    Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

    Clock shaper circuit for transition fault testing
    10.
    发明授权
    Clock shaper circuit for transition fault testing 有权

    公开(公告)号：US12216160B2

    公开(公告)日：2025-02-04

    申请号：US18182848

    申请日：2023-03-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Wilson Pradeep ,  Sriraj Chellappan ,  Shruti Gupta

    IPC: G01R31/317 ,  G01R31/3177 ,  G11C19/28 ,  H03K19/20

    Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

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