公开(公告)号：US20220165223A1

公开(公告)日：2022-05-26

申请号：US17388943

申请日：2021-07-29

Applicant: Texas Instruments Incorporated

Inventor： Stephen Phillip Savage ,  Harsh Dinesh Jhaveri

IPC: G09G3/34 ,  H03M7/30 ,  G09G5/399 ,  G09G5/395

Abstract: Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

公开(公告)号：US11716078B2

公开(公告)日：2023-08-01

申请号：US17709644

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Bondade ,  Maxim Franke ,  Stephen Phillip Savage ,  Mrinal Kanti Das ,  Johan Tjeerd Strydom

IPC: H03K17/082 ,  H03K17/687

CPC classification number: H03K17/0822 ,  H03K17/6871 ,  H03K2217/94

Abstract: In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.

公开(公告)号：US20230188130A1

公开(公告)日：2023-06-15

申请号：US17709644

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Bondade ,  Maxim Franke ,  Stephen Phillip Savage ,  Mrinal Kanti Das ,  Johan Tjeerd Strydom

IPC: H03K17/082 ,  H03K17/687

CPC classification number: H03K17/0822 ,  H03K17/6871 ,  H03K2217/94

Abstract: In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.

公开(公告)号：US20240087539A1

公开(公告)日：2024-03-14

申请号：US18516583

申请日：2023-11-21

Applicant: Texas Instruments Incorporated

Inventor： Stephen Phillip Savage ,  Harsh Dinesh Jhaveri

IPC: G09G3/34 ,  G09G5/395 ,  G09G5/399 ,  H03M7/30

CPC classification number: G09G3/346 ,  G09G5/395 ,  G09G5/399 ,  H03M7/30 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2370/00

Abstract: A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.

公开(公告)号：US20230280781A1

公开(公告)日：2023-09-07

申请号：US18115686

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Ryan Patrick Savage ,  Stephen Phillip Savage

IPC: G06F1/04 ,  G06F1/26

CPC classification number: G06F1/04 ,  G06F1/26

Abstract: An example apparatus includes a multiplexer; a first memory coupled to the multiplexer; a second memory coupled to the multiplexer, the second memory including a bi-level reset indicator, a multi-level reset indicator, and a duration indicator; a memory controller coupled to the multiplexer; and waveform generation circuitry coupled to the memory controller, the waveform generation circuitry including: a first power supply configured to receive the bi-level reset indicator; a second power supply configured to receive the multi-level reset indicator; and timing circuitry configured to receive the duration indicator.

公开(公告)号：US11862117B2

公开(公告)日：2024-01-02

申请号：US17388943

申请日：2021-07-29

Applicant: Texas Instruments Incorporated

Inventor： Stephen Phillip Savage ,  Harsh Dinesh Jhaveri

IPC: G09G5/395 ,  G09G3/34 ,  H03M7/30 ,  G09G5/399

CPC classification number: G09G3/346 ,  G09G5/395 ,  G09G5/399 ,  H03M7/30 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2370/00

Abstract: Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

公开(公告)号：US20230336172A1

公开(公告)日：2023-10-19

申请号：US18208345

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Bondade ,  Maxim Franke ,  Stephen Phillip Savage ,  Mrinal Kanti Das ,  Johan Tjeerd Strydom

IPC: H03K17/082 ,  H03K17/687

CPC classification number: H03K17/0822 ,  H03K17/6871 ,  H03K2217/94

Abstract: In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.