公开(公告)号：US20200043849A1

公开(公告)日：2020-02-06

申请号：US16050383

申请日：2018-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kuntal JOARDAR ,  Min CHU ,  Vijay KRISHNAMURTHY ,  Tikno HARJONO ,  Ankur CHAUHAN ,  Vinayak HEGDE ,  Manish SRIVASTAVA

IPC: H01L23/525 ,  H01L27/112 ,  G11C17/16

Abstract: An electronic device comprises a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sense transistor integrated in the first semiconductor die, the first sense transistor comprising a second gate and third and fourth terminals, the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor has a first temperature coefficient; a second sense transistor integrated in the first semiconductor die, the second sense transistor comprising a third gate and seventh and eighth terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor has a second temperature coefficient.

公开(公告)号：US20190204361A1

公开(公告)日：2019-07-04

申请号：US15859470

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tikno HARJONO ,  Vijay KRISHNAMURTHY ,  Min CHU ,  Kuntal JOARDAR ,  Gary Eugene DAUM ,  Subrato ROY ,  Vinayak HEGDE ,  Ankur CHAUHAN ,  Sathish VALLAMKONDA ,  Md Abidur RAHMAN ,  Eung Jung KIM

IPC: G01R15/14 ,  H01L27/06 ,  H01L49/02 ,  H01L25/18 ,  H03K17/567

CPC classification number: G01R15/146 ,  H01L25/18 ,  H01L27/0629 ,  H01L28/20 ,  H03K17/567

Abstract: An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.

公开(公告)号：US20250110171A1

公开(公告)日：2025-04-03

申请号：US18677217

申请日：2024-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhinay PATIL ,  Vinayak HEGDE ,  Umang AGARWAL

IPC: G01R31/28 ,  G01R35/00

Abstract: One example includes a circuit. The circuit includes a transistor device arranged between a first terminal and a second terminal and a transistor device controller configured to control operation of the transistor device. The circuit further includes a current limit controller that includes a current limit circuit configured to regulate an amplitude of operational current through the transistor device between the first and second terminals during a normal operating mode, and a testing system configured to conduct a calibration current provided by an automated testing equipment (ATE) device through an internal test resistor for the ATE device to determine a resistance value of the internal test resistor during a test mode to facilitate testing of the current limit circuit via a test current provided by the ATE device between the first and second terminals through the transistor device based on the determined resistance value of the internal test resistor.

公开(公告)号：US20230221742A1

公开(公告)日：2023-07-13

申请号：US18090861

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vinayak HEGDE ,  Rolly BARADIYA ,  Ankur CHAUHAN

IPC: G05F1/56 ,  G05F3/26 ,  G05F1/46

CPC classification number: G05F1/561 ,  G05F3/262 ,  G05F1/468

Abstract: In examples, an apparatus includes a FET, first and second voltage-to-current circuits, a current selection circuit, and a comparator. The FET has first and second segments. The first segment has a first gate coupled to the first voltage-to-current circuit, a first source, and a first drain. The second segment has a second gate coupled to the second voltage-to-current circuit, a second source coupled to the first source, and a second drain coupled to the first drain. The current selection circuit has a current selection circuit output and first and second current selection inputs. The first current selection circuit input is coupled to the first voltage-to-current circuit. The second current selection circuit input is coupled to the second voltage-to-current circuit. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current selection circuit output.