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1.发明申请公开(公告)号：US20200372164A1
公开(公告)日：2020-11-26
申请号：US16419753
申请日：2019-05-22
IPC分类号： G06F21/62
摘要： An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.
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2.发明申请公开(公告)号：US20230111755A1
公开(公告)日：2023-04-13
申请号：US18079237
申请日：2022-12-12
IPC分类号： H04N19/557 , H04N19/577 , G01S17/89 , G01S17/86 , H04N19/567
摘要： Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.
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公开(公告)号：US20230067264A1
公开(公告)日：2023-03-02
申请号：US18047439
申请日：2022-10-18
IPC分类号： G06F21/62
摘要： An apparatus includes a memory device and a microcontroller device integrated with the memory device. The microcontroller device is adapted to be communicatively coupled to a processor device and is configured to manage access by the processor device to data stored on the memory device. Managing access by the processor device to the data stored on the memory device includes setting an access permission for controlled data stored by the memory device based on authorization data stored in the memory device. Managing access by the processor device further includes receiving, from the processor device, a request to access the controlled data. Managing access by the processor device further includes determining whether to initiate access to the controlled data by the processor device based on the access permission.
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公开(公告)号：US20230385463A1
公开(公告)日：2023-11-30
申请号：US18326176
申请日：2023-05-31
发明人： Veeramanikandan RAJU
IPC分类号： G06F21/88 , G06F21/57 , H04W4/02 , H04W4/70 , H04L61/103 , H04W12/126
CPC分类号： G06F21/88 , G06F21/575 , H04W4/025 , H04W4/023 , H04W4/70 , H04L61/103 , H04W12/126 , G06F21/31
摘要： An end-user computing device can include a theft detector that maintains a registered host device list containing identifiers of at least one registered host device. The theft detector can have root access to operations of the end-user device and the theft detector can provides a secure reboot request in response to detecting a possible theft condition. The end-user computing device can also include a boot loader that executes a secure reboot of the end-user device in response to a secure reboot request from the theft detector. The secure reboot of the end-user device resets the end-user device to prevent access to the end-user device.
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公开(公告)号：US20230185679A1
公开(公告)日：2023-06-15
申请号：US18166787
申请日：2023-02-09
CPC分类号： G06F11/1616 , G06F11/1441 , G06F13/20 , G06F11/0757 , G06F11/0745 , G06F2201/805
摘要： A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.
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6.发明申请公开(公告)号：US20220060740A1
公开(公告)日：2022-02-24
申请号：US17520795
申请日：2021-11-08
IPC分类号： H04N19/557 , H04N19/577 , G01S17/89 , G01S17/86 , H04N19/567
摘要： Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.
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公开(公告)号：US20230326002A1
公开(公告)日：2023-10-12
申请号：US18333151
申请日：2023-06-12
发明人： Mihir Narendra MODY, JR. , Veeramanikandan RAJU , Niraj NANDAN , Samuel Paul VISALLI , Jason A.T. JONES , Kedar Satish CHITNIS , Gregory Raymond SHURTZ , Prithvi Shankar YEYYADI ANANTHA , Sriramakrishnan GOVINDARAJAN
CPC分类号： G06T7/0002 , G06T1/20 , G06T3/40 , H04N17/00 , G06T7/97 , G06T2207/10016 , G05B23/0259
摘要： Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.
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公开(公告)号：US20230097130A1
公开(公告)日：2023-03-30
申请号：US17482734
申请日：2021-09-23
IPC分类号： H03M1/06
摘要： An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC toa second digital conversion output from the ADC.
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公开(公告)号：US20220012312A1
公开(公告)日：2022-01-13
申请号：US17487517
申请日：2021-09-28
摘要： In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.
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公开(公告)号：US20190205508A1
公开(公告)日：2019-07-04
申请号：US16188560
申请日：2018-11-13
CPC分类号： G06F21/16 , G06N3/0472 , G06N20/00
摘要： In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.
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