公开(公告)号：US11300615B2

公开(公告)日：2022-04-12

申请号：US16220209

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Sundarrajan Rangachari ,  Prashanth Saraf

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/317

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

公开(公告)号：US20190317855A1

公开(公告)日：2019-10-17

申请号：US16453081

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G06F3/06 ,  G11C11/56 ,  G11C11/16 ,  G11C5/04 ,  H03M13/37 ,  H03M13/35 ,  H03M13/19 ,  G11C7/22 ,  G11C7/10

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US11709203B2

公开(公告)日：2023-07-25

申请号：US17690821

申请日：2022-03-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Sundarrajan Rangachari ,  Prashanth Saraf

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/317

CPC classification number: G01R31/318307 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/31813 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/31708

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

公开(公告)号：US10372531B2

公开(公告)日：2019-08-06

申请号：US15653749

申请日：2017-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G11C5/04 ,  G06F3/06 ,  G11C11/16 ,  G11C11/56 ,  H03M13/35 ,  G11C7/10 ,  G11C7/22

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.