公开(公告)号：US20250045040A1

公开(公告)日：2025-02-06

申请号：US18228462

申请日：2023-07-31

Applicant: Texas Instruments Incorporated

Inventor： Seth Rickard ,  Kristopher Ryan Burney ,  Alexander D'Abreu ,  Suyash Jain ,  Kumaran Vijayasankar

IPC: G06F8/654 ,  G06F8/658

Abstract: An example apparatus includes: interface circuitry; machine-readable instructions; and programmable circuitry configured to at least one of instantiate or execute the machine-readable instructions to: determine a number of memory sectors to shift an original image based on a length of extra data in an updated image in differential image data; shift the original image by the number of memory sectors to create a swap area, the swap area including the number of memory sectors; and construct the updated image based on the differential image data and the original image.

公开(公告)号：US11818048B2

公开(公告)日：2023-11-14

申请号：US17239244

申请日：2021-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kumaran Vijayasankar ,  Suyash Jain

IPC: H04L47/127 ,  H04L43/0882

CPC classification number: H04L47/127 ,  H04L43/0882

Abstract: Aspects of the disclosure provide for a computer program product comprising computer executable instructions. The instructions are executable by a controller of a network device to cause the controller to analyze data transmitted by the network device via a network for a programmed amount of time, determine a data transmission pattern based on the analysis, determine, based on the transmission pattern, a volume of expected data transmission during a period of time, and determine whether to transmit additional data based on a relationship between the volume of expected data transmission during the period of time and a bandwidth allocation of the network device during the period of time.

公开(公告)号：US20230370985A1

公开(公告)日：2023-11-16

申请号：US18195254

申请日：2023-05-09

Applicant: Texas Instruments Incorporated

Inventor： Seth Ryan Rickard ,  Kumaran Vijayasankar ,  Suyash Jain ,  Alexander Anthony D′Abreu

IPC: H04W56/00 ,  H04W24/10

CPC classification number: H04W56/0015 ,  H04W24/10

Abstract: An example apparatus includes interface circuitry, memory configured to store machine-readable instructions, and processing circuitry configured to at least one of instantiate or execute the machine-readable instructions. The example processing circuitry is configured to at least one of instantiate or execute the machine-readable instructions to determine a connectivity metric for a first device synchronized with a second device and cause, via the interface circuitry, transmission of the connectivity metric to a third device with which the first device is not synchronized. Additionally, the example processing circuitry is configured to at least one of instantiate or execute the machine-readable instructions to, based on a first communication from the third device, cause transmission of a second communication to the first device to cause the first device to synchronize with the third device.