公开(公告)号：US10297497B2

公开(公告)日：2019-05-21

申请号：US15658039

申请日：2017-07-24

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Sebastian Meier ,  Helmut Rinck ,  Kai-Alexander Schachtschneider ,  Fromund Metz ,  Mario Schmidpeter ,  Javier Gustavo Moreira

IPC分类号： H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213

摘要： In accordance with at least one embodiment of the disclosure, a method of patterning platinum on a substrate is disclosed. In an embodiment, an adhesive layer is deposited over the substrate, a sacrificial layer is deposited over the adhesive layer, and a patterned photoresist layer is formed over the sacrificial layer. Then, the sacrificial layer is patterned utilizing the photoresist layer as a mask such that at least a portion of the adhesive layer is exposed. Subsequently, the top and sidewall surfaces of the patterned sacrificial layer and the first portion of the adhesive layer are covered by a platinum layer. Finally, the sacrificial layer and a portion of the platinum layer covering the top and sidewall surfaces of the sacrificial layer are etched, thereby leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate.

公开(公告)号：US20210242029A1

公开(公告)日：2021-08-05

申请号：US17234833

申请日：2021-04-20

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck

IPC分类号： H01L21/306 ,  H01L21/308 ,  C23F1/44 ,  C23F1/30 ,  H01L21/24

摘要： There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.

公开(公告)号：US10714439B2

公开(公告)日：2020-07-14

申请号：US16107545

申请日：2018-08-21

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Nazila Dadvand ,  Helmut Rinck

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/78

摘要： A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.

公开(公告)号：US09230852B2

公开(公告)日：2016-01-05

申请号：US13775484

申请日：2013-02-25

申请人： Texas Instruments Incorporated ,  TEXAS INSTRUMENTS DEUTSCHLAND GmbH

发明人： Helmut Rinck ,  Fromund Metz ,  Jan Hermann Pape ,  Janet Riley

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/34 ,  H01L23/552 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L21/768 ,  H01L23/3171 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/552 ,  H01L24/05 ,  H01L2224/05554 ,  H01L2924/1461 ,  H01L2924/00

摘要： An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad. A metal capping layer includes an electrically conductive metal or an electrically conductive metal compound over at least the contact area to provide corrosion protection to the bond pad metal, which is in electrical contact with the bond pad metal. The metal capping layer can extend over structures other than the bond pads, such as to cover at least 80% of the area of the IC die to provide structures on the IC die protection from incident radiation.

摘要翻译： 集成电路（IC）管芯具有顶侧表面提供电路，其包括被配置为提供功能的有源电路，所述功能包括由耦合到所述电路中的节点的接合焊盘金属片形成的至少一个接合焊盘。 电介质钝化层位于衬底的顶侧表面上，提供暴露接合焊盘的接触区域。 金属覆盖层包括在至少接触区域上的导电金属或导电金属化合物，以向与接合焊盘金属电接触的接合焊盘金属提供腐蚀保护。 金属覆盖层可以在结合焊盘之外的结构上延伸，例如覆盖IC芯片的至少80％的面积，以提供IC芯片上的结构，防止入射辐射。

公开(公告)号：US11011381B2

公开(公告)日：2021-05-18

申请号：US16523867

申请日：2019-07-26

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck

IPC分类号： H01L21/306 ,  H01L21/308 ,  C23F1/44 ,  C23F1/30 ,  H01L21/24

摘要： There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.

公开(公告)号：US20200035500A1

公开(公告)日：2020-01-30

申请号：US16523867

申请日：2019-07-26

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/24 ,  C23F1/30 ,  C23F1/44

摘要： There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.

公开(公告)号：US09960135B2

公开(公告)日：2018-05-01

申请号：US14665799

申请日：2015-03-23

申请人： Texas Instruments Incorporated

发明人： Helmut Rinck ,  Gernot Bauer ,  Robert Zrile ,  Kai-Alexander Schachtschneider ,  Michael Otte ,  Harald Wiesner

IPC分类号： H01L21/28 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05558 ,  H01L2224/05657 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01078 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01051

摘要： A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

公开(公告)号：US20210313179A1

公开(公告)日：2021-10-07

申请号：US17347715

申请日：2021-06-15

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC分类号： H01L21/28 ,  H01L21/311 ,  C01G55/00 ,  H01L21/263 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285 ,  H01L23/00 ,  H01L49/02 ,  H01L23/532

摘要： A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

公开(公告)号：US11069530B2

公开(公告)日：2021-07-20

申请号：US16688060

申请日：2019-11-19

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC分类号： H01L21/44 ,  H01L21/28 ,  H01L21/311 ,  C01G55/00 ,  H01L21/263 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285 ,  H01L23/00 ,  H01L49/02 ,  H01L23/532 ,  H01L21/8238

摘要： A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

公开(公告)号：US20200083050A1

公开(公告)日：2020-03-12

申请号：US16688060

申请日：2019-11-19

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/263 ,  C01G55/00 ,  H01L21/311 ,  H01L23/532 ,  H01L21/768 ,  H01L29/66 ,  H01L49/02 ,  H01L23/00 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/02

摘要： A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.