公开(公告)号：US10402355B2

公开(公告)日：2019-09-03

申请号：US15890558

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US12056073B2

公开(公告)日：2024-08-06

申请号：US17946270

申请日：2022-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F12/1081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US20210160151A1

公开(公告)日：2021-05-27

申请号：US17164925

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Todd Christopher Hiers ,  Chunhua Hu

IPC: H04L12/24 ,  G06F3/0483 ,  G06F3/0486 ,  G06F30/30

Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

公开(公告)号：US10911323B2

公开(公告)日：2021-02-02

申请号：US15878978

申请日：2018-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Todd Christopher Hiers ,  Chunhua Hu

IPC: G06F3/00 ,  H04L12/24 ,  G06F3/0483 ,  G06F3/0486 ,  G06F30/30 ,  G06F3/01

Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

公开(公告)号：US11449444B2

公开(公告)日：2022-09-20

申请号：US16559154

申请日：2019-09-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US11418409B2

公开(公告)日：2022-08-16

申请号：US17164925

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Todd Christopher Hiers ,  Chunhua Hu

IPC: G06F3/00 ,  H04L41/22 ,  G06F3/0483 ,  G06F3/0486 ,  H04L41/12 ,  G06F30/30 ,  G06F3/01

Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.