公开(公告)号：US11449444B2

公开(公告)日：2022-09-20

申请号：US16559154

申请日：2019-09-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US10402355B2

公开(公告)日：2019-09-03

申请号：US15890558

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US11823759B2

公开(公告)日：2023-11-21

申请号：US17402706

申请日：2021-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Charles Lance Fuoco ,  Brian Karguth ,  Jay Bryan Reimer ,  Samuel Paul Visalli

IPC: G11C29/42 ,  G06F9/30 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F9/30029 ,  G06F11/1048

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.

公开(公告)号：US12056073B2

公开(公告)日：2024-08-06

申请号：US17946270

申请日：2022-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F12/1081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US11094392B2

公开(公告)日：2021-08-17

申请号：US16601303

申请日：2019-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Charles Lance Fuoco ,  Brian Karguth ,  Jay Bryan Reimer ,  Samuel Paul Visalli

IPC: G11C29/42 ,  G06F9/30 ,  G06F11/10 ,  G11C29/54

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.