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公开(公告)号:US11768784B2
公开(公告)日:2023-09-26
申请号:US17946675
申请日:2022-09-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chunhua Hu , Sanand Prasad
CPC classification number: G06F13/28 , G06F13/4221 , G06F2213/0026 , G06F2213/28
Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.
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公开(公告)号:US11449447B2
公开(公告)日:2022-09-20
申请号:US17139441
申请日:2020-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chunhua Hu , Sanand Prasad
Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.
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公开(公告)号:US10819334B2
公开(公告)日:2020-10-27
申请号:US16299544
申请日:2019-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chunhua Hu , Venkateswar Reddy Kowkutla , Charles Fuoco
IPC: H03K17/22
Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.
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公开(公告)号:US20180183434A1
公开(公告)日:2018-06-28
申请号:US15387683
申请日:2016-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Venkateswar Reddy Kowkutla , Erkan Bilhan , Sumant Dinkar Kale , Chunhua Hu
CPC classification number: H03K17/22 , G06F11/1441 , H03B5/32
Abstract: A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.
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5.
公开(公告)号:US12113612B2
公开(公告)日:2024-10-08
申请号:US17876662
申请日:2022-07-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chunhua Hu , Venkateswar Reddy Kowkutla , Eric Hansen , Denis Beaudoin , Thomas Anton Leyrer
CPC classification number: H04J3/0658 , H04J3/0641 , H04J3/0676 , H04J3/0679 , H04J3/0691 , H04J3/0667 , H04J3/0688 , H04L7/0083
Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
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公开(公告)号:US12056073B2
公开(公告)日:2024-08-06
申请号:US17946270
申请日:2022-09-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Brian Karguth , Chuck Fuoco , Chunhua Hu , Todd Christopher Hiers
IPC: G06F13/28 , G06F12/1081 , G06F13/42
CPC classification number: G06F13/28 , G06F12/1081 , G06F13/4282 , G06F2213/0026
Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.
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公开(公告)号:US20200328738A1
公开(公告)日:2020-10-15
申请号:US16912057
申请日:2020-06-25
Applicant: Texas Instruments Incorporated
Inventor: Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
IPC: H03K17/22 , G05B19/042 , G06F1/24 , G06F1/3296
Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.
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公开(公告)号:US10734993B2
公开(公告)日:2020-08-04
申请号:US15393513
申请日:2016-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
IPC: G05B19/042 , G06F1/24 , G06F1/3296 , H03K17/22 , H03K17/30
Abstract: The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.
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公开(公告)号:US20180191343A1
公开(公告)日:2018-07-05
申请号:US15393513
申请日:2016-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
IPC: H03K17/22 , H03K17/30 , G05B19/042
CPC classification number: H03K17/22 , G05B19/042 , G05B2219/21119 , G06F1/24 , G06F1/3296 , H03K17/30
Abstract: The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.
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10.
公开(公告)号:US20180181179A1
公开(公告)日:2018-06-28
申请号:US15387680
申请日:2016-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
IPC: G06F1/28
Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.
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