Broadband frequency multiplier with harmonic suppression

    公开(公告)号:US12132488B2

    公开(公告)日:2024-10-29

    申请号:US18148845

    申请日:2022-12-30

    CPC classification number: H03K5/00006 G06F1/08 H03H7/0115 H03H7/0161

    Abstract: Described embodiments include a circuit having a quadrature phase generator circuit having differential generator inputs, in-phase differential generator outputs and quadrature-phase differential generator outputs. A first frequency multiplier circuit has first differential multiplier inputs and a first multiplier output, wherein the first differential multiplier inputs are coupled to the in-phase differential generator outputs. A second frequency multiplier circuit has second differential multiplier inputs and a second multiplier output. The second multiplier differential inputs are coupled to the quadrature-phase differential generator outputs. A transformer includes a primary inductor and a secondary inductor, wherein the primary inductor is coupled between the first and second multiplier outputs, and the second inductor is coupled between an output voltage terminal and a ground terminal.

    SINGLE STAGE FREQUENCY MULTIPLIER USING DIFFERENT TYPES OF SIGNAL MIXING MODES

    公开(公告)号:US20220352853A1

    公开(公告)日:2022-11-03

    申请号:US17694953

    申请日:2022-03-15

    Abstract: A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.

    CHARGE PUMP
    3.
    发明申请

    公开(公告)号:US20210203329A1

    公开(公告)日:2021-07-01

    申请号:US16731739

    申请日:2019-12-31

    Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

    BIDIRECTIONAL DATA TRANSMISSION OVER ISOLATION MEDIUM

    公开(公告)号:US20240430147A1

    公开(公告)日:2024-12-26

    申请号:US18341482

    申请日:2023-06-26

    Abstract: An apparatus includes a controller having differential modulation control outputs and is configured to provide differential modulation signals having a particular frequency at the differential modulation control outputs. A differential modulator circuit is coupled between first differential terminals and second differential terminals. The differential modulator circuit has differential modulation control inputs coupled to the differential modulation control outputs. The differential modulator circuit is configured to: modulate first differential signals at the first differential terminals with the differential modulation signals having the particular frequency, provide the modulated first differential signals at the second differential terminals, modulate second differential signals at the second differential terminals with the differential modulation signals having the particular frequency, and provide the modulated second differential signals at the first differential terminals.

    DIFFERENTIAL ELECTRICAL BALANCE DUPLEXERS
    9.
    发明公开

    公开(公告)号:US20240072839A1

    公开(公告)日:2024-02-29

    申请号:US17823292

    申请日:2022-08-30

    CPC classification number: H04B1/525 H04B1/0057 H03H7/463 H04L5/14

    Abstract: Electrical balance duplexers (EBDs). An example EBD includes a differential TX port coupled to a first coil, a differential RX port coupled to a second coil, a differential ANT port coupled to a third coil, and a differential BAL port coupled to a fourth coil. In some cases, the first and second coils are arranged such that magnetic flux cancellation is achieved between the two, thus isolating the TX port from the RX port. In some cases, DC isolation exists between the coils. During operation, the first coil may electromagnetically couple with the third coil and the fourth coil, and the second coil may electromagnetically couple with the third coil and the fourth coil. In some example cases, the first and second coils are each in their own metallization layer, and the third and fourth coils are in the same layer.

Patent Agency Ranking