公开(公告)号：US11171601B1

公开(公告)日：2021-11-09

申请号：US16942230

申请日：2020-07-29

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Theertham ,  Srikanth Manian ,  Uday Kiran Meda

IPC: H03B5/12 ,  H03L7/099

Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

公开(公告)号：US11509266B2

公开(公告)日：2022-11-22

申请号：US17493922

申请日：2021-10-05

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Theertham ,  Srikanth Manian ,  Uday Kiran Meda

IPC: H03B5/12 ,  H03L7/099

Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

公开(公告)号：US11290118B2

公开(公告)日：2022-03-29

申请号：US17128791

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Theertham ,  Jagdish Chand ,  Yogesh Darwhekar ,  Subhashish Mukherjee ,  Jayawardan Janardhanan ,  Uday Kiran Meda ,  Arpan Sureshbhai Thakkar ,  Apoorva Bhatia ,  Pranav Kumar

IPC: H03L7/23 ,  H03M1/66 ,  H03L7/085 ,  H03L7/099

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.