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公开(公告)号：US20240235564A9
公开(公告)日：2024-07-11
申请号：US18081028
申请日：2022-12-14
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar
CPC classification number: H03M1/0604 , H03K21/026
Abstract: A digital-to-time converter (DTC) circuit. The DTC circuit includes a charge node. A variable current source has a source input and a source output. The source input is coupled to a DTC digital input and the source output is coupled to the charge node. A capacitor has a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the charge node. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the charge node, the second comparator input is coupled to a reference voltage terminal, and the comparator output is coupled to a DTC output. A pre-charge circuit has a pre-charge control input and a pre-charge output. The pre-charge control input is coupled to a DTC pre-charge input and the pre-charge output is coupled to the capacitor.
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公开(公告)号：US10608853B1
公开(公告)日：2020-03-31
申请号：US16130087
申请日：2018-09-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yogesh Darwhekar , Pranav Kumar , Arpan Thakkar , Naveen Mahadev , Srikanth Manian
IPC: H04L27/00 , H04L27/38 , H04L27/152 , H04L27/148
Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.
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公开(公告)号：US10382078B2
公开(公告)日：2019-08-13
申请号：US15486909
申请日：2017-04-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Yogesh Darwhekar , Nagaraj V. Dixit , Raghu Ganesan
IPC: H04B1/10 , H04B1/16 , H04B17/318 , H03L7/099 , H03J7/00 , H03L7/087 , H03L7/18 , H04B1/12 , H03G3/30
Abstract: At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium.
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公开(公告)号：US20170187515A1
公开(公告)日：2017-06-29
申请号：US15388407
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Srikanth Manian , Srinivas Theertham , Jagdish Chand Goyal , Robert Karl Butler
CPC classification number: H04L27/261 , H03L7/099 , H03L7/1976
Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.
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公开(公告)号：US20150004909A1
公开(公告)日：2015-01-01
申请号：US14318606
申请日：2014-06-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhishek Agrawal , Yogesh Darwhekar , Gireesh Rajendran
CPC classification number: G05F1/613 , H02M7/217 , H04B5/0031
Abstract: A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak detector is coupled to the antenna and receives the differential output signal over the differential path, A first comparator receives a voltage output of the peak detector and a first voltage. A second comparator receives the voltage output of the peak detector and a second voltage. A digital state machine receives an output of the first comparator and an output of the second comparator. A plurality of shunt NMOS transistors receives an output of the digital state machine. The digital state machine is configured to control the number of shunt NMOS transistors that are activated to maintain the voltage output of the peak detector between the first voltage and the second voltage.
Abstract translation: 数字分流调节器在天线处接收射频（RF）信号，其在差分路径上产生差分输出信号。 峰值检测器耦合到天线，并通过差分路径接收差分输出信号。第一比较器接收峰值检测器的电压输出和第一电压。 第二比较器接收峰值检测器的电压输出和第二电压。 数字状态机接收第一比较器的输出和第二比较器的输出。 多个并联NMOS晶体管接收数字状态机的输出。 数字状态机被配置为控制被激活的并联NMOS晶体管的数量，以将峰值检测器的电压输出保持在第一电压和第二电压之间。
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Patent Agency Ranking
公开(公告)号：US20240137031A1
公开(公告)日：2024-04-25
申请号：US18081028
申请日：2022-12-14
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar
CPC classification number: H03M1/0604 , H03K21/026
Abstract: A digital-to-time converter (DTC) circuit. The DTC circuit includes a charge node. A variable current source has a source input and a source output. The source input is coupled to a DTC digital input and the source output is coupled to the charge node. A capacitor has a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the charge node. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the charge node, the second comparator input is coupled to a reference voltage terminal, and the comparator output is coupled to a DTC output. A pre-charge circuit has a pre-charge control input and a pre-charge output. The pre-charge control input is coupled to a DTC pre-charge input and the pre-charge output is coupled to the capacitor.
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公开(公告)号：US20230179215A1
公开(公告)日：2023-06-08
申请号：US17541781
申请日：2021-12-03
Applicant: Texas Instruments Incorporated
Inventor： Jayawardan Janardhanan , Yogesh Darwhekar , Subhashish Mukherjee
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
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公开(公告)号：US11290118B2
公开(公告)日：2022-03-29
申请号：US17128791
申请日：2020-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Theertham , Jagdish Chand , Yogesh Darwhekar , Subhashish Mukherjee , Jayawardan Janardhanan , Uday Kiran Meda , Arpan Sureshbhai Thakkar , Apoorva Bhatia , Pranav Kumar
Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.
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公开(公告)号：US10658357B2
公开(公告)日：2020-05-19
申请号：US15990880
申请日：2018-05-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pranav Kumar , Yogesh Darwhekar
IPC: H01L27/06 , H03K19/018 , H01L29/73
Abstract: A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor.
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10.发明授权公开(公告)号：US10236826B1
公开(公告)日：2019-03-19
申请号：US16000972
申请日：2018-06-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yogesh Darwhekar , Apoorva Bhatia , Subhashish Mukherjee
Abstract: A down converter, including first and second biasing circuits, mixer, and transformer coupled to receive amplifier output signal. The first and second biasing circuits each include a biasing transistor and a first and second node, respectively. Mixer includes first and second transistors coupled to first node and third and fourth transistors coupled to second node. The second and fourth transistors are coupled to a third node. The first and third transistors are coupled to a fourth node. Mixer also includes a first resistor coupled to the fourth node and a supply voltage node and a second resistor coupled to the third node and a supply voltage node. Transformer includes a primary winding coupled to receive the amplifier output signal and to a supply voltage and a secondary winding coupled to mixer and first biasing circuit at first node and coupled to mixer and second biasing circuit at second node.
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