-
公开(公告)号：US11676884B2
公开(公告)日：2023-06-13
申请号：US17242121
申请日：2021-04-27
IPC分类号： H01L23/495 , H01L23/522
CPC分类号： H01L23/49503 , H01L23/4951 , H01L23/49548 , H01L23/5227 , H01L2224/48247 , H01L2924/0002
摘要： A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
-
公开(公告)号：US10483909B2
公开(公告)日：2019-11-19
申请号：US15173044
申请日：2016-06-03
摘要： Methods and apparatus are disclosed to generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.
-
公开(公告)号：US10284238B1
公开(公告)日：2019-05-07
申请号：US16004503
申请日：2018-06-11
摘要： A radio frequency transmitter includes a digital-to-analog converter (DAC), a load circuit, and a modulator circuit. The load circuit is coupled to an output of the DAC. The modulator circuit is coupled to the DAC and the load circuit. The modulator circuit includes a driver circuit configured to provide a bias voltage to the load circuit, and an amplifier configured to receive an output of the DAC biased by an output of the load circuit.
-
公开(公告)号：US20180068894A1
公开(公告)日：2018-03-08
申请号：US15343557
申请日：2016-11-04
摘要： An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.
-
5.发明授权公开(公告)号：US09722536B2
公开(公告)日：2017-08-01
申请号：US14518001
申请日：2014-10-20
IPC分类号： H03B5/12
CPC分类号： H03B5/1212 , H03B5/1228 , H03B5/1265
摘要： Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.
-
6.发明申请Cantilevered Leadframe Support Structure for Magnetic Wireless Transfer Between Integrated Circuit Dies 审中-公开集成电路模块之间磁性无线传输的悬臂引线框支撑结构公开(公告)号：US20150325501A1
公开(公告)日：2015-11-12
申请号：US14275762
申请日：2014-05-12
IPC分类号： H01L23/495
CPC分类号： H01L23/49503 , H01L23/4951 , H01L23/5227 , H01L2224/48247 , H01L2924/0002
摘要： A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
摘要翻译： 耦合器件使用引线框提供电隔离，引线框被配置为以共面方式支撑两个集成电路芯片。 每个芯片都包含一个电感耦合线圈。 引线框架包括用于附接接合线以耦合到两个集成电路芯片的一组接合焊盘。 两个分离的芯片连接焊盘支持两个芯片。 每个管芯附接垫被配置成用多个悬臂指状物支撑两个集成电路芯片中的一个。
-
公开(公告)号：US20150138995A1
公开(公告)日：2015-05-21
申请号：US14082785
申请日：2013-11-18
CPC分类号： H04W24/02 , H04L5/0048 , H04L27/0014 , H04L27/34 , H04L2027/0016 , H04L2027/0087
摘要： According to an aspect of the present disclosure, a baseband signal and a pilot signal are combined for a transmission. The combined signal is then translated to higher frequency band by mixing a local oscillator signal and the combined signal. On the receiver, the pilot signal is used to remove the phase noise in the baseband signal, as both baseband signal and the pilot signal are affected/modified by substantially the same phase noise. In one embodiment, the pilot signal may be selected either centered outside the bandwidth of the base band signal or centered inside the bandwidth of the base band signal with enough guard band around it so that it can be filtered out using filters. The pilot signal is used in a similar fashion to eliminate the effect of the phase noise introduced by the local oscillator present in the tester in testing the receiver device.
摘要翻译： 根据本公开的一个方面，组合基带信号和导频信号用于传输。 然后通过混合本地振荡器信号和组合信号将组合的信号转换到更高的频带。 在接收机上，导频信号用于去除基带信号中的相位噪声，因为基带信号和导频信号都受到基本上相同的相位噪声的影响/修改。 在一个实施例中，导频信号可以选择在基带信号的带宽之外的中心，或者位于基带信号的带宽内，其周围具有足够的保护带，使得可以使用滤波器滤除导频信号。 导频信号以类似的方式使用，以消除在测试接收机设备中存在于测试仪中的本地振荡器引入的相位噪声的影响。
-
公开(公告)号：US11843392B2
公开(公告)日：2023-12-12
申请号：US17541781
申请日：2021-12-03
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
-
公开(公告)号：US11615040B2
公开(公告)日：2023-03-28
申请号：US17390428
申请日：2021-07-30
摘要： A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
-
公开(公告)号：US11581897B1
公开(公告)日：2023-02-14
申请号：US17377698
申请日：2021-07-16
摘要： A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.
-
-
-
-
-
-
-
-
-
搜索结果
59 条记录 (耗时 0.02 秒)
