公开(公告)号：US09384826B2

公开(公告)日：2016-07-05

申请号：US14562056

申请日：2014-12-05

Applicant: Texas Instruments Incorporated

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/418 ,  G11C11/4094 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

Abstract translation: 在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位 沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压， 预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控​​制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电 将被执行。

公开(公告)号：US20160314832A1

公开(公告)日：2016-10-27

申请号：US15199167

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

Abstract translation: 在所述示例中，存储器控制器电路控制对SRAM电路的访问。 预充电模式控制电路输出：到SRAM电路的突发模式使能信号，指示将沿着选定的一行SRAM单元的一系列SRAM单元被访问; 向SRAM电路提供预充电第一模式信号，指示将发生沿着所选行的第一次访问; 以及向SRAM电路提供预充电最后模式信号，指示将发生沿着所选行的最后访问。 SRAM电路包括以行和列排列以存储数据的SRAM单元的阵列。 每个SRAM单元耦合到：沿着一行SRAM单元的相应字线; 和相应的一对互补位线。

公开(公告)号：US09734896B2

公开(公告)日：2017-08-15

申请号：US15199167

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

公开(公告)号：US20160163379A1

公开(公告)日：2016-06-09

申请号：US14562056

申请日：2014-12-05

Applicant: Texas Instruments Incorporated

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

Abstract translation: 在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位 沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压， 预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控​​制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电 将被执行。