公开(公告)号：US09384826B2

公开(公告)日：2016-07-05

申请号：US14562056

申请日：2014-12-05

Applicant: Texas Instruments Incorporated

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/418 ,  G11C11/4094 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

Abstract translation: 在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位 沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压， 预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控​​制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电 将被执行。

公开(公告)号：US20160314832A1

公开(公告)日：2016-10-27

申请号：US15199167

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

Abstract translation: 在所述示例中，存储器控制器电路控制对SRAM电路的访问。 预充电模式控制电路输出：到SRAM电路的突发模式使能信号，指示将沿着选定的一行SRAM单元的一系列SRAM单元被访问; 向SRAM电路提供预充电第一模式信号，指示将发生沿着所选行的第一次访问; 以及向SRAM电路提供预充电最后模式信号，指示将发生沿着所选行的最后访问。 SRAM电路包括以行和列排列以存储数据的SRAM单元的阵列。 每个SRAM单元耦合到：沿着一行SRAM单元的相应字线; 和相应的一对互补位线。

公开(公告)号：US20250004100A1

公开(公告)日：2025-01-02

申请号：US18391109

申请日：2023-12-20

Applicant: Texas Instruments Incorporated

Inventor： Jasbir Singh ,  Premkumar Seetharaman ,  Sandeep Rao ,  Rashmi Sachan

IPC: G01S7/35 ,  G06F3/06

Abstract: An example device includes a memory that includes a first portion and a second portion, memory control circuitry structured to receive a first set of data associated with a first radar chirp, receive a second set of data associated with a second radar chirp, store a first subset of the first set of data in the first portion of the memory, store a first subset of the second set of data in the first portion of the memory adjacent to the first subset of the first set of data, and store a second subset of the first set of data and a second subset of the second set of data in the second portion of the memory.

公开(公告)号：US09613685B1

公开(公告)日：2017-04-04

申请号：US14940715

申请日：2015-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Premkumar Seetharaman ,  Vinod Menezes

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.

公开(公告)号：US09734896B2

公开(公告)日：2017-08-15

申请号：US15199167

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

公开(公告)号：US09496024B1

公开(公告)日：2016-11-15

申请号：US14974945

申请日：2015-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivasa Raghavan Sridhara ,  Sanjeev Kumar Suman ,  Premkumar Seetharaman ,  Keshav Bhaktavatson Chintamani ,  Atul Ramakant Lele ,  Raviprakash S. Rao ,  Parvinder Kumar Rana ,  Ajith Subramonia ,  Vipul K. Singhal ,  Malav Shrikant Shah ,  Bharath Kumar Poluri

IPC: G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C11/413

Abstract: A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Abstract translation: 芯片上的系统（SOC）包括处理器和耦合到处理器的存储器系统。 存储器系统包括静态随机存取存储器（SRAM）存储体和存储器控制器。 SRAM库包括耦合到SRAM阵列电源的第一开关和SRAM阵列中的SRAM存储单元的晶体管的源极。 SRAM库还包括耦合到NWELL电源和SRAM存储单元的大部分晶体管的第二开关。 第二开关被配置为在SRAM阵列上电期间在第一开关闭合之前关闭。

公开(公告)号：US20160163379A1

公开(公告)日：2016-06-09

申请号：US14562056

申请日：2014-12-05

Applicant: Texas Instruments Incorporated

Inventor： Per Torstein Roine ,  Vinod Menezes ,  Mahesh Mehendale ,  Vamsi Gullapalli ,  Premkumar Seetharaman

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/412

Abstract: In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

Abstract translation: 在本申请的各方面中，提供了用于存储数据的电路，其中包括静态随机存取存储器（SRAM）电路，其可操作以将数据存储在以行和列布置的SRAM单元电路阵列中，每个SRAM单元耦合到一对互补位 沿着SRAM单元电路的列布置的线以及SRAM存储器电路中的一个或多个预充电电路，其耦合到一对或多对互补位线，并且可操作用于对互补位线对充电至预充电电压， 预充电控制信号。 SRAM电路内的预充电控制信号可操作以使SRAM电路内的耦合晶体管响应于从SRAM电路外部的存储器控​​制器电路输出的模式信号将一对互补位线耦合到预充电电压，指示位线预充电 将被执行。