公开(公告)号：US10367511B2

公开(公告)日：2019-07-30

申请号：US16036221

申请日：2018-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota ,  Mark Baxter Weaver ,  William Bright ,  Jiankun Hu

IPC: H03K21/00 ,  H03K23/00 ,  H03L7/08 ,  G06F1/12 ,  H03L7/16

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

公开(公告)号：US10050632B2

公开(公告)日：2018-08-14

申请号：US15395489

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota ,  Mark Baxter Weaver ,  William Bright ,  Jiankun Hu

IPC: H03K21/00 ,  H03K23/00 ,  H03L7/08

CPC classification number: H03L7/08 ,  G06F1/12 ,  H03L7/16

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

公开(公告)号：US11444587B2

公开(公告)日：2022-09-13

申请号：US17124785

申请日：2020-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yang Xu ,  William Bright ,  Hasibur Rahman

IPC: H03F3/04 ,  H03K5/00 ,  H03F3/45

Abstract: A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

公开(公告)号：US12057814B2

公开(公告)日：2024-08-06

申请号：US17880142

申请日：2022-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yang Xu ,  William Bright ,  Hasibur Rahman

IPC: H03F3/04 ,  H03F1/34

CPC classification number: H03F3/04 ,  H03F2200/129 ,  H03F2200/165

Abstract: A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

公开(公告)号：US20220385244A1

公开(公告)日：2022-12-01

申请号：US17880142

申请日：2022-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yang Xu ,  William Bright ,  Hasibur Rahman

IPC: H03F3/04

Abstract: A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

公开(公告)号：US20220200544A1

公开(公告)日：2022-06-23

申请号：US17124785

申请日：2020-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yang Xu ,  William Bright ,  Hasibur Rahman

IPC: H03F3/04

Abstract: A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.