公开(公告)号：US12074517B2

公开(公告)日：2024-08-27

申请号：US17137086

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Reza Sharifi ,  Timothy Patrick Pauletti ,  Keliu Shu ,  Mark Baxter Weaver

IPC: H02M3/156 ,  H02M1/00 ,  H02M3/157 ,  H02M1/14 ,  H02M3/158

CPC classification number: H02M3/1563 ,  H02M1/0032 ,  H02M3/156 ,  H02M3/157 ,  H02M1/14 ,  H02M3/1582

Abstract: A DC-DC regulator system includes a power circuit which has a first input coupled to receive an input voltage, a second input coupled to receive a control signal and an output to provide a regulated output voltage. The system includes a control circuit which has a first input coupled to receive the regulated output voltage, a second input coupled to receive a reference voltage, a first output to provide the control signal, and a second output to provide a converter clock signal. The system includes an out-of-audio circuit which has a first input coupled to receive a minimum threshold frequency signal, a second input coupled to receive the converter clock signal, a third input coupled to the power circuit output, and a fourth input coupled to receive a bandwidth control clock signal.

公开(公告)号：US20220209669A1

公开(公告)日：2022-06-30

申请号：US17137086

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Reza Sharifi ,  Timothy Patrick Pauletti ,  Keliu Shu ,  Mark Baxter Weaver

IPC: H02M3/156 ,  H02M3/157

Abstract: A DC-DC regulator system includes a power circuit which has a first input coupled to receive an input voltage, a second input coupled to receive a control signal and an output to provide a regulated output voltage. The system includes a control circuit which has a first input coupled to receive the regulated output voltage, a second input coupled to receive a reference voltage, a first output to provide the control signal, and a second output to provide a converter clock signal. The system includes an out-of-audio circuit which has a first input coupled to receive a minimum threshold frequency signal, a second input coupled to receive the converter clock signal, a third input coupled to the power circuit output, and a fourth input coupled to receive a bandwidth control clock signal.

公开(公告)号：US10367511B2

公开(公告)日：2019-07-30

申请号：US16036221

申请日：2018-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota ,  Mark Baxter Weaver ,  William Bright ,  Jiankun Hu

IPC: H03K21/00 ,  H03K23/00 ,  H03L7/08 ,  G06F1/12 ,  H03L7/16

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

公开(公告)号：US10050632B2

公开(公告)日：2018-08-14

申请号：US15395489

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota ,  Mark Baxter Weaver ,  William Bright ,  Jiankun Hu

IPC: H03K21/00 ,  H03K23/00 ,  H03L7/08

CPC classification number: H03L7/08 ,  G06F1/12 ,  H03L7/16

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.