公开(公告)号：US20190088719A1

公开(公告)日：2019-03-21

申请号：US15910786

申请日：2018-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Minoru ODA ,  Akira YOTSUMOTO ,  Kotaro NODA

IPC: H01L27/24 ,  H01L23/528 ,  H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A storage device including a transistor portion including a transistor, a plurality of interlayer insulating films provided above the transistor portion, a plurality of first conductive layers provided respectively between the plurality of interlayer insulating films, and a second conductive layer extending through the plurality of interlayer insulating films and the plurality of first conductive layers, the second conductive layer having one end electrically connected to the transistor portion, and a part that extends beyond a portion of the transistor portion.

公开(公告)号：US20200098630A1

公开(公告)日：2020-03-26

申请号：US16290851

申请日：2019-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Minoru ODA

IPC: H01L21/768 ,  H01L27/092 ,  H01L27/12 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/8238

Abstract: A semiconductor device includes a semiconductor substrate, a source or drain layer provided in the semiconductor substrate, a gate insulation layer provided on a surface of the semiconductor substrate, and a gate electrode that is provided on the gate insulation layer. The semiconductor device further includes a first contact that is provided on the source or drain layer, the first contact including a stacked body in which a plurality of first layers and one or more second layers are alternately stacked, and a second contact that faces at least one of a side surface and an upper surface of the first contact disposed on the source or drain layer.

公开(公告)号：US20180277598A1

公开(公告)日：2018-09-27

申请号：US15705219

申请日：2017-09-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Minoru ODA ,  Akira YOTSUMOTO ,  Nobuyuki MOMO ,  Kotaro NODA

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/085 ,  H01L45/1683

Abstract: A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction. The intermediate region is positioned between the first region and the second region. The control electrode is disposed at a position so that the control electrode faces the intermediate region via an insulating film. The semiconductor pillar is provided so that a minimum width of the intermediate region in a second direction perpendicular to the first direction is narrower than a first width of the first region in the second direction and a second width of the second region in the second direction.