公开(公告)号：US20200286828A1

公开(公告)日：2020-09-10

申请号：US16564584

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji HOSOTANI ,  Fumitaka ARAI ,  Keisuke NAKATSUKA ,  Nobuyuki MOMO ,  Motohiko FUJIMATSU

IPC: H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.

公开(公告)号：US20200098829A1

公开(公告)日：2020-03-26

申请号：US16289651

申请日：2019-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke ARAYASHIKI ,  Nobuyuki MOMO ,  Motohiko FUJIMATSU ,  Akira HOKAZONO

IPC: H01L27/24

Abstract: A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US20200303400A1

公开(公告)日：2020-09-24

申请号：US16502877

申请日：2019-07-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka ARAI ,  Masakazu GOTO ,  Masaki KONDO ,  Keiji HOSOTANI ,  Nobuyuki MOMO

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11573

Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.

公开(公告)号：US20180277598A1

公开(公告)日：2018-09-27

申请号：US15705219

申请日：2017-09-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Minoru ODA ,  Akira YOTSUMOTO ,  Nobuyuki MOMO ,  Kotaro NODA

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/085 ,  H01L45/1683

Abstract: A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction. The intermediate region is positioned between the first region and the second region. The control electrode is disposed at a position so that the control electrode faces the intermediate region via an insulating film. The semiconductor pillar is provided so that a minimum width of the intermediate region in a second direction perpendicular to the first direction is narrower than a first width of the first region in the second direction and a second width of the second region in the second direction.