公开(公告)号：US20190088316A1

公开(公告)日：2019-03-21

申请号：US15906453

申请日：2018-02-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuki INUZUKA ,  Tsuneo INABA ,  Takayuki MIYAZAKI ,  Takeshi SUGIMOTO

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

公开(公告)号：US20190295640A1

公开(公告)日：2019-09-26

申请号：US16128446

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuki INUZUKA ,  Yoshinori SUZUKI

IPC: G11C13/00

Abstract: According to one embodiment, a semiconductor memory device, includes a resistance change type memory cell; a first charge section into which a charge based on a current flowing in the memory cell is charged; a second charge section coupled to the first charge section via a switch element; a sense amplifier configured to determine data stored in the memory cell based on the charge charged into the second charge section; and a control circuit configured to control the first charge section, the second charge section, and the sense amplifier.

公开(公告)号：US20200082880A1

公开(公告)日：2020-03-12

申请号：US16285104

申请日：2019-02-25

Applicant: Toshiba Memory Corporation

Inventor： Yuki INUZUKA ,  Takaaki NAKAZATO

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.