公开(公告)号：US20190189693A1

公开(公告)日：2019-06-20

申请号：US16282482

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/2436

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20180175111A1

公开(公告)日：2018-06-21

申请号：US15899465

申请日：2018-02-20

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/2436

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20210384259A1

公开(公告)日：2021-12-09

申请号：US17407896

申请日：2021-08-20

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20200243606A1

公开(公告)日：2020-07-30

申请号：US16845538

申请日：2020-04-10

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20190088316A1

公开(公告)日：2019-03-21

申请号：US15906453

申请日：2018-02-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuki INUZUKA ,  Tsuneo INABA ,  Takayuki MIYAZAKI ,  Takeshi SUGIMOTO

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

公开(公告)号：US20180096725A1

公开(公告)日：2018-04-05

申请号：US15825699

申请日：2017-11-29

Applicant: Toshiba Memory Corporation

Inventor： Takeshi SUGIMOTO

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.