公开(公告)号：US20190081101A1

公开(公告)日：2019-03-14

申请号：US15905256

申请日：2018-02-26

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shingo NAKAZAWA ,  Tsuneo INABA ,  Hiroyuki TAKENAKA

IPC: H01L27/22 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L27/222 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/81 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481

Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

公开(公告)号：US20190109196A1

公开(公告)日：2019-04-11

申请号：US16211891

申请日：2018-12-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takeshi SONEHARA ,  Erika KODAMA ,  Nobutaka NAKAMURA ,  Tsuneo INABA ,  Koichi NAKAYAMA

IPC: H01L29/417 ,  H01L27/11556 ,  H01L27/1158 ,  H01L23/528

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

公开(公告)号：US20200295087A1

公开(公告)日：2020-09-17

申请号：US16558822

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Atsushi KAWASUMI ,  Tsuneo INABA

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.

公开(公告)号：US20190259438A1

公开(公告)日：2019-08-22

申请号：US16400048

申请日：2019-05-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsuya KISHI ,  Tsuneo INABA ,  Daisuke WATANABE ,  Masahiko NAKAYAMA ,  Nobuyuki OGATA ,  Masaru TOKO ,  Hisanori AIKAWA ,  Jyunichi OZEKI ,  Toshihiko NAGASE ,  Young Min EEH ,  Kazuya SAWADA

IPC: G11C11/16 ,  G11C7/10

Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.

公开(公告)号：US20180075895A1

公开(公告)日：2018-03-15

申请号：US15456031

申请日：2017-03-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsuya KISHI ,  Tsuneo INABA ,  Daisuke WATANABE ,  Masahiko NAKAYAMA ,  Nobuyuki OGATA ,  Masaru TOKO ,  Hisanori AIKAWA ,  Jyunichi OZEKI ,  Toshihiko NAGASE ,  Young Min EEH ,  Kazuya SAWADA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/1096 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.

公开(公告)号：US20190259436A1

公开(公告)日：2019-08-22

申请号：US16400095

申请日：2019-05-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsuneo INABA

IPC: G11C11/16 ,  G11C7/10 ,  G11C7/04

Abstract: A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.

公开(公告)号：US20190088316A1

公开(公告)日：2019-03-21

申请号：US15906453

申请日：2018-02-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuki INUZUKA ,  Tsuneo INABA ,  Takayuki MIYAZAKI ,  Takeshi SUGIMOTO

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.

公开(公告)号：US20180277743A1

公开(公告)日：2018-09-27

申请号：US15702339

申请日：2017-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsuneo INABA ,  Tatsuya KISHI ,  Masahiko NAKAYAMA

IPC: H01L43/02 ,  G11C11/16 ,  G11C7/10 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C7/1096 ,  G11C11/1675 ,  G11C11/1697 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.

公开(公告)号：US20180075892A1

公开(公告)日：2018-03-15

申请号：US15455906

申请日：2017-03-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Tsuneo INABA ,  Yutaka SHIRAI

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/04 ,  G11C7/065 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/28

Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.

公开(公告)号：US20190103440A1

公开(公告)日：2019-04-04

申请号：US16109363

申请日：2018-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsuneo INABA ,  Hiroyuki TAKENAKA

IPC: H01L27/24 ,  G11C13/00 ,  G11C5/02 ,  G11C5/06

CPC classification number: H01L27/2454 ,  G11C5/025 ,  G11C5/063 ,  G11C7/12 ,  G11C8/14 ,  G11C13/0002 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.