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公开(公告)号：US20200074713A1
公开(公告)日：2020-03-05
申请号：US16116158
申请日：2018-08-29
申请人： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
发明人： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
摘要： Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
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公开(公告)号：US20180081429A1
公开(公告)日：2018-03-22
申请号：US15268494
申请日：2016-09-16
申请人： TOMAS G. AKENINE-MOLLER , ROBERT M. TOTH , INGO WALD , ADITYA S. YANAMANDRA , BRENT E. INSKO , MICHAEL APODACA , PRASOONKUMAR SURTI
发明人： TOMAS G. AKENINE-MOLLER , ROBERT M. TOTH , INGO WALD , ADITYA S. YANAMANDRA , BRENT E. INSKO , MICHAEL APODACA , PRASOONKUMAR SURTI
CPC分类号： G06F3/013 , G06F3/011 , G06F3/012 , G06T1/20 , G06T3/0093 , G06T15/005 , G06T19/006 , G06T2200/24
摘要： A virtual reality apparatus and method are described. For example, one embodiment of an apparatus comprises: a compute cluster comprising global illumination circuitry and/or logic to perform global illumination operations on graphics data in response to execution of a virtual reality application and to responsively generate a stream of samples; a filtering/compression module to perform filtering and/or compression operations on the stream of samples to generate filtered/compressed samples; a network interface to communicatively couple the compute cluster to a network, the filtered/compressed samples to be streamed over the network; a render node to receive the filtered/compressed samples streamed over the network, the render node comprising: decompression circuitry/logic to decompress the filtered/compressed samples to generate decompressed samples; a sample buffer to store the decompressed samples; and sample insertion circuitry/logic to asynchronously insert samples into a light field rendered by a light field rendering circuit/logic.
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公开(公告)号：US20140176541A1
公开(公告)日：2014-06-26
申请号：US13726362
申请日：2012-12-24
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T11/40 , G06T15/005 , G06T2200/12 , G06T2210/08
摘要： Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.
摘要翻译： 各种实施例通常涉及用于在为样本存储所渲染的颜色数据值时使得清除颜色的颜色数据值的存储被延迟的技术。 一种设备包括处理器电路和存储器，用于存储使得处理器电路从取自对象的三维模型的多个样本呈现像素的指令，所述像素对应于包括多个颜色存储位置的像素样本数据， 每个由数字标识符标识，并且其包括多个样本颜色索引，每个样本颜色索引对应于样本以指向至少一个颜色存储位置; 并且以所选择的顺序分配颜色存储位置，以将所有样本颜色索引中的二进制索引值的可能组合的子集定义为无效组合。 描述和要求保护其他实施例。
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公开(公告)号：US20190096095A1
公开(公告)日：2019-03-28
申请号：US15719472
申请日：2017-09-28
申请人： KIRAN C. VEERNAPU , BENJAMIN R. PLETCHER , YOAV HAREL , SANTOSH SANGUMANI , PRASOONKUMAR SURTI , ABHISHEK R. APPU
发明人： KIRAN C. VEERNAPU , BENJAMIN R. PLETCHER , YOAV HAREL , SANTOSH SANGUMANI , PRASOONKUMAR SURTI , ABHISHEK R. APPU
摘要： An apparatus and method for pre-decompression filtering of compressed texel data. For example, one embodiment of a method comprises: determining whether compressed texel data requested for a graphics processing operation is a first type of texel data or a second type of texel data; if the compressed texel data is of a first type then: decompressing the compressed texel data prior to filtering to generate decompressed unfiltered texel data, and filtering the decompressed unfiltered texel data to produce first filtered and decompressed texel data; and if the compressed texel data is of a second type then: concurrently filtering and decompressing the texel data to produce second filtered and decompressed texel data, or filtering the texel data before decompression to generate filtered compressed texel data and then decompressing the filtered compressed texel data to produce the second filtered and decompressed texel data; and providing the first filtered and decompressed texel data or the second filtered and decompressed texel data to the graphics processing operation.
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公开(公告)号：US20190066356A1
公开(公告)日：2019-02-28
申请号：US15693084
申请日：2017-08-31
CPC分类号： G06T15/005 , G06T1/20 , G06T1/60 , G06T15/205 , G06T15/40 , G06T15/80 , G06T2200/28
摘要： An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware.
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公开(公告)号：US20180082465A1
公开(公告)日：2018-03-22
申请号：US15268496
申请日：2016-09-16
申请人： PRASOONKUMAR SURTI , TOMAS G. AKENINE-MOLLER , DAVID COWPERTHWAITE , KEVIN TIAN , PETER L. DOYLE , BRENT INSKO , ADAM T. LAKE
发明人： PRASOONKUMAR SURTI , TOMAS G. AKENINE-MOLLER , DAVID COWPERTHWAITE , KEVIN TIAN , PETER L. DOYLE , BRENT INSKO , ADAM T. LAKE
CPC分类号： G06T15/005 , G06T1/20 , G06T1/60 , G06T15/405 , G06T15/503 , G06T2207/20021 , G06T2210/12
摘要： A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.
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公开(公告)号：US20180082464A1
公开(公告)日：2018-03-22
申请号：US15268495
申请日：2016-09-16
申请人： TOMAS G. AKENINE-MOLLER , ROBERT M. TOTH , BRENT E. INSKO , PETER L. DOYLE , PRASOONKUMAR SURTI , MAIYURAN SUBRAMANIAM , CARL JACOB MUNKBERG , FRANZ PETRIK CLARBERG , JON N. HASSELGREN
发明人： TOMAS G. AKENINE-MOLLER , ROBERT M. TOTH , BRENT E. INSKO , PETER L. DOYLE , PRASOONKUMAR SURTI , MAIYURAN SUBRAMANIAM , CARL JACOB MUNKBERG , FRANZ PETRIK CLARBERG , JON N. HASSELGREN
IPC分类号： G06T15/00 , G06T17/10 , G06T15/80 , G06T15/30 , G06T15/40 , G06T17/20 , G06T15/04 , G06T15/20
CPC分类号： G06T15/005 , G06T15/04 , G06T15/205 , G06T15/30 , G06T15/405 , G06T15/80 , G06T17/10 , G06T17/20 , G06T2210/12
摘要： A graphics processing apparatus and method are described. For example, one embodiment of a graphics processing apparatus comprises: an input assembler of a graphics pipeline to determine a first set of triangles to be drawn based on application-provided parameters; a depth buffer to store depth data related to the first set of triangles; a vertex shader to perform position-only vertex shading operations on the first set of triangles in response to an indication that the graphics pipeline is to initially operate in a depth-only mode; a culling and clipping module to read depth values from the depth buffer to identify those triangles in the first set of triangles which are fully occluded by other objects in a current frame and to generate culling data usable to cull occluded triangles, the culling and clipping module to associate the culling data with a replay token to be used to identify a subsequent rendering pass through the graphics pipeline; the input assembler, upon detecting the replay token in the subsequent rendering pass, to access the culling data associated therewith to remove culled triangles from the first set of triangles to generate a second set of triangles; the vertex shader to perform full vertex shading operations on the second set of triangles during the subsequent rendering pass, the replay token to be destroyed during or following the subsequent rendering pass.
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公开(公告)号：US20160307362A1
公开(公告)日：2016-10-20
申请号：US14691517
申请日：2015-04-20
CPC分类号： G06T15/005
摘要： An apparatus and method are described for performing efficient depth test operations. For example, an apparatus in accordance with one embodiment comprises: a depth cache to store a plurality of cache lines containing depth data to be used for graphics processing operations; depth test logic to determine a current depth test function associated with a read operation and to read a cache line from a depth cache while there are still outstanding writes to the cache line if the read operation and write operation are associated with the same depth test function, the depth test logic to perform a first depth test using the data read from the cache line, the first depth test to fail or pass pixels based on a predicted range of depth values.
摘要翻译： 描述了用于执行有效的深度测试操作的装置和方法。 例如，根据一个实施例的装置包括：深度缓存，用于存储包含要用于图形处理操作的深度数据的多个高速缓存行; 深度测试逻辑以确定与读取操作相关联的当前深度测试功能，并且如果读取操作和写入操作与相同深度测试功能相关联，则仍然存在对高速缓存行的未写入，则从深度缓存读取高速缓存行 深度测试逻辑，用于使用从高速缓存行读取的数据来执行第一深度测试，第一深度测试基于深度值的预测范围来失败或传递像素。
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公开(公告)号：US20180293786A1
公开(公告)日：2018-10-11
申请号：US15482692
申请日：2017-04-07
申请人： BRENT E. INSKO , PRASOONKUMAR SURTI
发明人： BRENT E. INSKO , PRASOONKUMAR SURTI
CPC分类号： G06T15/405 , G06T15/005 , H04N13/279 , H04N13/344 , H04N13/383 , H04N13/398
摘要： An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
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10.发明申请公开(公告)号：US20180292897A1
公开(公告)日：2018-10-11
申请号：US15482694
申请日：2017-04-07
申请人： INGO WALD , BRENT E. INSKO , PRASOONKUMAR SURTI , KUN TIAN , ADAM T. LAKE , YAO ZU EDDIE DONG , PETER L. DOYLE
发明人： INGO WALD , BRENT E. INSKO , PRASOONKUMAR SURTI , KUN TIAN , ADAM T. LAKE , YAO ZU EDDIE DONG , PETER L. DOYLE
摘要： One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.
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