公开(公告)号：USD488441S1

公开(公告)日：2004-04-13

申请号：US29161788

申请日：2002-06-05

申请人： Tadahiko Ogawa ,  Koyuru Nakano

设计人： Tadahiko Ogawa ,  Koyuru Nakano

公开(公告)号：US06809923B2

公开(公告)日：2004-10-26

申请号：US10361846

申请日：2003-02-11

申请人： Masashi Isozumi ,  Tsunetoshi Oba ,  Takashi Horie ,  Tadahiko Ogawa

发明人： Masashi Isozumi ,  Tsunetoshi Oba ,  Takashi Horie ,  Tadahiko Ogawa

IPC分类号： H05K500

CPC分类号： H05K7/1432

摘要： The power supply unit comprises a power supply circuit accommodating chamber A and an arithmetic circuit accommodating chamber B partitioned from each other by a partition wall, and power supply circuit substrates 7 and 8 and an arithmetic circuit substrate 12 are accommodated in the power supply circuit accommodating chamber A and the arithmetic circuit accommodating chamber B, respectively. A connector of the power supply circuit substrate 8 and a connector of the arithmetic circuit substrate 12 are connected to each other through the partition wall of the power supply circuit accommodating chamber A and the arithmetic circuit accommodating chamber B.

摘要翻译： 电源单元包括电源电路容纳室A和通过分隔壁彼此分隔的运算电路容纳室B，并且电源电路基板7,8和运算电路基板12容纳在电源电路容纳 室A和运算电路容纳室B。 电源电路基板8的连接器和运算电路基板12的连接器通过电源电路容纳室A的分隔壁和运算电路容纳室B相互连接。

公开(公告)号：USD467821S1

公开(公告)日：2002-12-31

申请号：US29147237

申请日：2001-08-27

申请人： Tadahiko Ogawa

设计人： Tadahiko Ogawa

公开(公告)号：US5406567A

公开(公告)日：1995-04-11

申请号：US75798

申请日：1993-06-14

申请人： Tadahiko Ogawa

发明人： Tadahiko Ogawa

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H04B17/00

CPC分类号： G01R31/318505 ,  G01R31/31701

摘要： In a semiconductor integrated logic circuit, latch circuits are provided to hold the input signal supplied to a random logic circuit just before an operation mode is switched from a normal operation mode to a test operation mode. During the test operation mode, the latched signals are continued to be supplied to random logic circuit so that the operation condition of a internal circuit of the random logic circuit is maintained as it is. Therefore, when the circuit is returned from the test operation mode to the normal operation mode, the circuit operation of the internal circuit of the random logic circuit continuing from the circuit operation in the previous normal operation condition can be obtained.

摘要翻译： 在半导体集成逻辑电路中，提供锁存电路以在将操作模式从正常操作模式切换到测试操作模式之前保持提供给随机逻辑电路的输入信号。 在测试操作模式期间，锁存的信号被继续提供给随机逻辑电路，使得随机逻辑电路的内部电路的操作状态原样保持。 因此，当电路从测试操作模式返回到正常操作模式时，可以获得在先前的正常操作条件下继续从电路操作继续的随机逻辑电路的内部电路的电路操作。

公开(公告)号：US06373686B1

公开(公告)日：2002-04-16

申请号：US09639994

申请日：2000-08-16

申请人： Tadahiko Ogawa ,  Hajime Takakuwa ,  Hiroyuki Yamamoto ,  Kiyotaka Tomioka

发明人： Tadahiko Ogawa ,  Hajime Takakuwa ,  Hiroyuki Yamamoto ,  Kiyotaka Tomioka

IPC分类号： H02B104

CPC分类号： H01H9/287 ,  H01H11/0006 ,  H01H27/00

摘要： An object is to provide a key protection structure for an electronic apparatus which can prevent a preset value of a switch from being intentionally changed by the user or the like. When setting of a first switch 21 is ended, a tool shutter operation portion 72 of a lock key 70 is inserted into a first shutter operation hole 61. The tool shutter operation portion 72 is then engaged with an engaging recess 45 of a first shutter 40. Thereafter, the lock key 70 is rotated, so that the first shutter 40 is rotated. A covering portion 44 of the shutter is therefore moved immediately above the first switch 21 to close a first switch operation hole 58, whereby the first switch 21 can be locked (key-protected) so as not to be externally operated.

摘要翻译： 本发明的目的是提供一种用于电子设备的键保护结构，其可防止开关的预设值被用户有意地改变。当第一开关21的设置结束时，工具快门操作部分72 锁定键70被插入到第一快门操作孔61中。然后，工具快门操作部分72与第一遮板40的接合凹部45接合。此后，锁定键70旋转，使得第一遮板40为 旋转 因此，快门的覆盖部分44在第一开关21的正上方移动以关闭第一开关操作孔58，由此第一开关21可被锁定（密钥保护），以便不被外部操作。

公开(公告)号：USD568242S1

公开(公告)日：2008-05-06

申请号：US29266687

申请日：2006-09-27

申请人： Tadahiko Ogawa

设计人： Tadahiko Ogawa

公开(公告)号：US06600525B1

公开(公告)日：2003-07-29

申请号：US09450711

申请日：1999-11-30

申请人： Daisuke Sawai ,  Tadahiko Ogawa ,  Hajime Takakuwa ,  Moriaki Koyama ,  Tomonori Hishikawa ,  Takayuki Arai

发明人： Daisuke Sawai ,  Tadahiko Ogawa ,  Hajime Takakuwa ,  Moriaki Koyama ,  Tomonori Hishikawa ,  Takayuki Arai

IPC分类号： G02F11333

CPC分类号： H05K5/0086 ,  H01M2/1044 ,  H01M2/1055

摘要： In an electronic component including an outer housing and a control unit inserted within the outer housing, the control unit includes a base, a printed circuit board mounted on the base, a battery holder mounted on the base for removably holding a coin-shaped battery which includes terminals connected with the printed circuit board to be connected with positive and negative poles of the battery, a liquid crystal display mounted on the base and connected with the printed circuit board, and a backlight unit mounted on the base and connected with the printed circuit board, whereby the battery may be easily replaced and the insulation distance between the battery and electronic parts on the printed circuit board is sufficiently ensured and a broad space may be ensured for arrangement of the electronic parts on the printed circuit board.

摘要翻译： 在包括插入在外壳内的外壳和控制单元的电子部件中，控制单元包括基座，安装在基座上的印刷电路板，安装在基座上的电池座，用于可拆卸地保持硬币形电池， 包括与印刷电路板连接的端子以与电池的正极和负极连接，安装在基座上并与印刷电路板连接的液晶显示器，以及安装在基座上并与印刷电路连接的背光单元 由此可以容易地更换电池，并且充分确保电池与印刷电路板上的电子部件之间的绝缘距离，并且可以确保用于在印刷电路板上布置电子部件的宽广的空间。

公开(公告)号：US06310491B1

公开(公告)日：2001-10-30

申请号：US09411834

申请日：1999-10-04

申请人： Tadahiko Ogawa

发明人： Tadahiko Ogawa

IPC分类号： H03K19173

CPC分类号： H03K3/0375 ,  H03K3/012

摘要： A sequential logic circuit having active and sleep modes prevents stored information from being lost immediately after the transition from a sleep mode to an active mode. This sequential logic circuit includes a latch circuit having an input terminal to which an input signal is applied, an output terminal from which and output signal is derived, and a set and/or reset terminal to which a set and/or reset signal is applied. The latch circuit has an active mode where a latch function is operable and a sleep mode where the latch function is inoperable, one of which is alternatively selected. The output signal is set or reset to have a specific logic state by the set or reset signal having a specific logic level applied to the set or reset terminal in the active mode. The sequential logic circuit further includes circuitry for preventing the set or reset signal from being applied to the set or reset terminal in the sleep mode, thereby avoiding loss of information or data latched in the latch circuit prior to transition to the sleep mode from the active mode. Thus, the information-latch operation in both of the modes is ensured.

摘要翻译： 具有活动和睡眠模式的顺序逻辑电路防止在从休眠模式转换到活动模式之后立即丢失存储的信息。 该顺序逻辑电路包括一个锁存电路，该锁存电路具有输入信号被施加的输入端，从其输出和输出信号的输出端，以及一个设置和/或复位信号被施加到的置位和/或复位端 。 锁存电路具有其中锁存功能可操作的活动模式和锁定功能不可操作的休眠模式，其中一个被选择。 输出信号被设置或复位为具有特定的逻辑状态，该设置或复位信号具有在激活模式下施加到置位或复位端子的特定逻辑电平。 顺序逻辑电路还包括用于在睡眠模式下防止设置或复位信号施加到设置或复位终端的电路，从而避免在从活动过渡到睡眠模式之前锁存在锁存电路中的信息或数据丢失 模式。 因此，确保了两种模式中的信息锁存操作。

公开(公告)号：US20070064536A1

公开(公告)日：2007-03-22

申请号：US11217746

申请日：2005-09-01

申请人： Tadahiko Ogawa

发明人： Tadahiko Ogawa

IPC分类号： G01V1/00

CPC分类号： G01V1/003

摘要： By nondestructively detecting a condition of ground 3 to be surveyed by using surface wave exploration means 4, using data analysis means 5 to calculate an S-wave velocity structure of the ground based on data detected by the surface wave exploration means 4, identifying a soil phase distribution of the ground by using a soil phase criteria table that is preset about a correspondence between S-wave velocities and soil phases based on a calculated S-wave velocity structure, and identifying an N-value distribution of the ground by using an N-value conversion expression or an N-value conversion table that is preset about a correspondence between S-wave velocities and N-values, an absorbed/released unit heat quantity per unit thickness of the ground 3, which provides a parameter, is estimated on the basis of the soil phase distribution and the N-value distribution that are identified by using a heat quantity conversion table that is preset about a relationship between the soil phase and a heat quantity and a relationship between the N-values and a heat quantity.

摘要翻译： 通过使用表面波探测装置4非破坏性地检测要测量的地面3的状况，利用数据分析装置5根据表面波探测装置4检测的数据计算地面的S波速度结构，识别土壤 通过使用基于计算的S波速度结构预先设定的关于S波速度和土壤相位之间的对应关系的土壤相位准则表来研究地面的相分布，以及通过使用N值来识别地面的N值分布 - 值变换表达式或关于S波速度和N值之间的对应关系的N值转换表，提供参数的地面3的每单位厚度的吸收/释放单位热量被估计为 土壤相分布和N值分布的基础，通过使用预设关于土壤相和土壤相关关系的热量转换表来识别 热量和N值与热量之间的关系。

公开(公告)号：US06246265B1

公开(公告)日：2001-06-12

申请号：US09330161

申请日：1999-06-11

申请人： Tadahiko Ogawa

发明人： Tadahiko Ogawa

IPC分类号： A03K19096

CPC分类号： H03K19/00315

摘要： A semiconductor integrated logic circuit device with a sequential circuit includes a transferring section, an inverting section, a bistable circuit section, and a blocking section. The transferring section is provided between first and second nodes, and transfers a data signal from the first node to the second node in response to a clock signal. The inverting section is provided between the second node and a third node, and inverts the data signal on the second node to output on the third node as an inverted data signal. The bistable circuit section is connected to the second and third nodes, and holds the data signal. The blocking section is provided between the bistable circuit and the first node, and blocks off sub-threshold leakage current.

摘要翻译： 具有顺序电路的半导体集成逻辑电路器件包括转移部分，反转部分，双稳态电路部分和阻断部分。 转移部分设置在第一和第二节点之间，并且响应于时钟信号将数据信号从第一节点传送到第二节点。 反相部分设置在第二节点和第三节点之间，并且将第二节点上的数据信号反相，以在第三节点上作为反相数据信号输出。 双稳态电路部分连接到第二和第三节点，并保持数据信号。 阻塞部分设置在双稳态电路和第一节点之间，并阻断次阈值漏电流。