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公开(公告)号:US06844232B2
公开(公告)日:2005-01-18
申请号:US10679483
申请日:2003-10-07
申请人: Tae Ho Choi , Jae Yeong Kim
发明人: Tae Ho Choi , Jae Yeong Kim
IPC分类号: H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号: H01L29/66825 , H01L21/28273 , H01L29/42336 , H01L29/7885
摘要: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.
摘要翻译: 闪速存储器件的单元晶体管包括半导体衬底,源极区,漏极区,浮置栅极,栅极间绝缘层和控制栅极,其中浮置栅极具有尖端突出到端部 源区域。 随着对源极区域和控制栅极施加擦除电压,在浮动栅极的尖端上产生强电场。 因此,可以提高单元晶体管的擦除效率。
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公开(公告)号:US06709925B1
公开(公告)日:2004-03-23
申请号:US10316904
申请日:2002-12-12
申请人: Tae Ho Choi , Jae Yeong Kim
发明人: Tae Ho Choi , Jae Yeong Kim
IPC分类号: H01L21336
CPC分类号: H01L21/28282 , H01L21/28273 , H01L29/42324
摘要: A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.
摘要翻译: 提供了分闸式闪存单元及其制造方法。 在衬底上形成隧道氧化物层之后,在隧道氧化物层的一部分上形成导电材料的峰值浮置栅极层。 在峰值浮置栅极层上形成栅极间绝缘层和控制栅极层,然后顺序蚀刻控制栅极层,栅极间绝缘层,峰值浮置栅极层和隧道氧化物层,以产生 控制栅极,栅极间绝缘区域,峰值浮置栅极和隧道氧化物区域。 最后,通过使用自对准技术将源极和漏极限定为邻接隧道氧化物区域。
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