公开(公告)号：USRE41205E1

公开(公告)日：2010-04-06

申请号：US10952576

申请日：2004-09-28

申请人： Jae-Yeong Kim

发明人： Jae-Yeong Kim

IPC分类号： H01L21/8236 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/6659

摘要： The present invention relates to a method of fabricating a semiconductor device which reduces The leakage current by controlling an etch of a field oxide layer when a contact hole is formed. The present invention includes the steps of forming a in a semiconductor device is reduced. A field oxide layer defining an active area and a field area is formed on a semiconductor substrateof a first conductive type, forming a . A gate is formed on the an active area of the semiconductor substrate. by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductor are formed on the substrate in use of using the gate as a mask, forming a . A first insulating interlayer layer is formed on the semiconductor substrate by depositing an insulator of which having the heat expansion coefficient and lattice mismatch that are less than those of the semiconductor substrateto cover the field oxide layer and the gate, forming a . A second insulating interlayer layer is formed on the first insulating interlayer layer by depositing another insulator of which having an etch rate that is different from that of the first insulating interlayer, forming a layer. A third insulating interlayer layer is formed on the second insulating interlayer layer by depositing yet another insulator of which having an etch rate that is different from that of the second insulating interlayer, and forming a first contact hole layer. First and second contact holes exposing the gate and heavily doped regions respectively are formed by patterning the third to first insulating interlayer successively by photolithography layers.

摘要翻译： 本发明涉及制造半导体器件的方法，该半导体器件通过在形成接触孔时控制场氧化物层的蚀刻来减小漏电流。 本发明包括减少形成半导体器件的步骤。 在第一导电类型的半导体衬底上形成限定有源区和场区的场氧化物层，形成。 栅极形成在半导体衬底的有源区上。 通过在半导体衬底和栅极之间插入栅极绝缘层，在使用栅极作为掩模的情况下，在衬底上形成在半导体中形成第二导电类型的杂质区域，形成。 通过沉积具有比半导体衬底小的热膨胀系数和晶格失配的绝缘体覆盖场氧化物层和栅极，形成第一绝缘层间层，形成在半导体衬底上。 通过沉积具有不同于第一绝缘中间层的蚀刻速率的另一绝缘体形成层，在第一绝缘层间层上形成第二绝缘层间层。 通过沉积具有不同于第二绝缘中间层的蚀刻速率的另一绝缘体并形成第一接触孔层，在第二绝缘层间层上形成第三绝缘层间层。 通过光刻层将第三至第一绝缘夹层连续地图案化，分别形成暴露栅极和重掺杂区域的第一和第二接触孔。

公开(公告)号：US06844232B2

公开(公告)日：2005-01-18

申请号：US10679483

申请日：2003-10-07

申请人： Tae Ho Choi ,  Jae Yeong Kim

发明人： Tae Ho Choi ,  Jae Yeong Kim

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7885

摘要： A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

摘要翻译： 闪速存储器件的单元晶体管包括半导体衬底，源极区，漏极区，浮置栅极，栅极间绝缘层和控制栅极，其中浮置栅极具有尖端突出到端部 源区域。 随着对源极区域和控制栅极施加擦除电压，在浮动栅极的尖端上产生强电场。 因此，可以提高单元晶体管的擦除效率。

公开(公告)号：US06709925B1

公开(公告)日：2004-03-23

申请号：US10316904

申请日：2002-12-12

申请人： Tae Ho Choi ,  Jae Yeong Kim

发明人： Tae Ho Choi ,  Jae Yeong Kim

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42324

摘要： A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

摘要翻译： 提供了分闸式闪存单元及其制造方法。 在衬底上形成隧道氧化物层之后，在隧道氧化物层的一部分上形成导电材料的峰值浮置栅极层。 在峰值浮置栅极层上形成栅极间绝缘层和控制栅极层，然后顺序蚀刻控制栅极层，栅极间绝缘层，峰值浮置栅极层和隧道氧化物层，以产生 控制栅极，栅极间绝缘区域，峰值浮置栅极和隧道氧化物区域。 最后，通过使用自对准技术将源极和漏极限定为邻接隧道氧化物区域。