公开(公告)号：US06709925B1

公开(公告)日：2004-03-23

申请号：US10316904

申请日：2002-12-12

申请人： Tae Ho Choi ,  Jae Yeong Kim

发明人： Tae Ho Choi ,  Jae Yeong Kim

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42324

摘要： A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

摘要翻译： 提供了分闸式闪存单元及其制造方法。 在衬底上形成隧道氧化物层之后，在隧道氧化物层的一部分上形成导电材料的峰值浮置栅极层。 在峰值浮置栅极层上形成栅极间绝缘层和控制栅极层，然后顺序蚀刻控制栅极层，栅极间绝缘层，峰值浮置栅极层和隧道氧化物层，以产生 控制栅极，栅极间绝缘区域，峰值浮置栅极和隧道氧化物区域。 最后，通过使用自对准技术将源极和漏极限定为邻接隧道氧化物区域。

公开(公告)号：US06844232B2

公开(公告)日：2005-01-18

申请号：US10679483

申请日：2003-10-07

申请人： Tae Ho Choi ,  Jae Yeong Kim

发明人： Tae Ho Choi ,  Jae Yeong Kim

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7885

摘要： A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

摘要翻译： 闪速存储器件的单元晶体管包括半导体衬底，源极区，漏极区，浮置栅极，栅极间绝缘层和控制栅极，其中浮置栅极具有尖端突出到端部 源区域。 随着对源极区域和控制栅极施加擦除电压，在浮动栅极的尖端上产生强电场。 因此，可以提高单元晶体管的擦除效率。

公开(公告)号：US07153742B2

公开(公告)日：2006-12-26

申请号：US11024193

申请日：2004-12-29

申请人： Tae Ho Choi

发明人： Tae Ho Choi

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： A flash memory device fabrication method is disclosed. A disclosed method comprises: forming an oxide layer on a substrate; depositing a first polysilicon on the entire surface of the oxide layer and patterning the first polysilicon; depositing an insulating layer on the entire surface of the first polysilicon and patterning the insulating layer to expose the first polysilicon; depositing a second polysilicon on the entire surface of the resulting structure and patterning the second polysilicon; removing the insulating layer; depositing a dielectric layer on the entire surface of the resulting structure; and depositing a third polysilicon on the entire surface of the dielectric layer.

摘要翻译： 公开了一种闪存器件制造方法。 所公开的方法包括：在衬底上形成氧化物层; 在所述氧化物层的整个表面上沉积第一多晶硅并对所述第一多晶硅进行构图; 在所述第一多晶硅的整个表面上沉积绝缘层并且图案化所述绝缘层以露出所述第一多晶硅; 在所得结构的整个表面上沉积第二多晶硅并图案化第二多晶硅; 去除绝缘层; 在所得结构的整个表面上沉积介电层; 以及在所述电介质层的整个表面上沉积第三多晶硅。

公开(公告)号：US20080149995A1

公开(公告)日：2008-06-26

申请号：US12068162

申请日：2008-02-04

申请人： Tae Ho Choi

发明人： Tae Ho Choi

IPC分类号： H01L29/788 ,  H01L21/8239

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.

摘要翻译： 一种制造非易失性存储器件的方法，包括在半导体衬底中形成多个器件隔离层以限定多个有源区，在半导体衬底上依次沉积绝缘层和第一导电层，以及在半导体衬底上形成硬掩模图案 第一导电层。 该方法还包括通过使用硬掩模图案作为掩模蚀刻第一导电层来在绝缘层上形成多个浮置栅极，在包括浮置栅极和绝缘层的半导体衬底上形成隧道绝缘层，并且沉积第二 隧道绝缘层上的导电层。 该方法还包括通过蚀刻第二导电层来形成跨越有源区的多个控制栅电极，通过进行离子注入在半导体衬底中形成源区和漏区，并在漏极区中形成接触。

公开(公告)号：US07348242B2

公开(公告)日：2008-03-25

申请号：US11024848

申请日：2004-12-30

申请人： Tae Ho Choi

发明人： Tae Ho Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.

公开(公告)号：US07247917B2

公开(公告)日：2007-07-24

申请号：US11023314

申请日：2004-12-27

申请人： Tae Ho Choi

发明人： Tae Ho Choi

IPC分类号： H01L29/78

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Nonvolatile semiconductor memory devices and methods of manufacturing the same are disclosed. A disclosed nonvolatile semiconductor memory cell includes a semiconductor substrate; first and second semiconductor cells positioned on the semiconductor substrate at a distance from each other; a first source and a second source adjacent the first and second semiconductor cells; a first drain contact between the first and second semiconductor cells; first and second cap dielectrics formed on the first and second semiconductor cells, respectively; first and second sidewall spacers formed on sidewalls of the first and second semiconductor cells, respectively; an inter metal dielectric layer covering the first and second cap dielectrics and the first and second sidewall spacers, a drain contact hole exposing the drain; and a second drain contact connected to the first drain contact through the drain contact hole.

摘要翻译： 公开了非易失性半导体存储器件及其制造方法。 所公开的非易失性半导体存储单元包括半导体衬底; 位于半导体衬底上彼此间隔一定距离的第一和第二半导体单元; 邻近第一和第二半导体单元的第一源极和第二源极; 第一和第二半导体单元之间的第一漏极接触; 分别形成在第一和第二半导体单元上的第一和第二盖电介质; 分别形成在第一和第二半导体单元的侧壁上的第一和第二侧壁间隔物; 覆盖第一和第二盖电介质以及第一和第二侧壁间隔物的金属间介电层，暴露漏极的漏极接触孔; 以及通过漏极接触孔连接到第一漏极接触的第二漏极接触。