公开(公告)号：US20060261844A1

公开(公告)日：2006-11-23

申请号：US11417970

申请日：2006-05-04

申请人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

发明人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： An impedance control circuit for use in a semiconductor device reduces an impedance mismatch between pull-up and pull-down resistances without increasing a resolution. The impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data. The impedance controller performs a comparison and counting operation so that the first and second output values of the impedance detector become approximated to a predetermined reference value, and generates the pull-up and pull-down control code data. Impedance mismatch between pull-up and pull-down resistances is reduced to half of a digital control resolution, substantially reducing transmission error or adverse effects on a setup/hold window of a receiver.

摘要翻译： 用于半导体器件中的阻抗控制电路减小上拉和下拉电阻之间的阻抗失配，而不增加分辨率。 阻抗控制电路包括阻抗检测器，输出驱动器和阻抗控制器。 阻抗检测器对连接在外部确定电阻器和上拉晶体管阵列之间的检测焊盘产生第一输出值，并将第二输出值输出到公共连接在上拉和下拉晶体管阵列之间的电阻分压器端子 响应于上拉控制代码数据和下拉控制代码数据。 输出驱动器具有公共连接的上拉和下拉晶体管阵列，以及连接到输出驱动器的上拉和下拉晶体管阵列的补偿单元，以补偿上拉和下拉的量化误差 下载控制代码数据。 阻抗控制器执行比较和计数操作，使得阻抗检测器的第一和第二输出值近似为预定的参考值，并产生上拉和下拉控制代码数据。 上拉和下拉电阻之间的阻抗失配降低到数字控制分辨率的一半，大大降低了对接收机的设置/保持窗口的传输误差或不利影响。

公开(公告)号：US07548086B2

公开(公告)日：2009-06-16

申请号：US11417970

申请日：2006-05-04

申请人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

发明人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K5/12

CPC分类号： H03K19/0005

摘要： An impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data. The impedance controller performs a comparison and counting operation so that the first and second output values of the impedance detector become approximated to a predetermined reference value, and generates the pull-up and pull-down control code data.

摘要翻译： 阻抗控制电路包括阻抗检测器，输出驱动器和阻抗控制器。 阻抗检测器对连接在外部确定电阻器和上拉晶体管阵列之间的检测焊盘产生第一输出值，并将第二输出值输出到公共连接在上拉和下拉晶体管阵列之间的电阻分压器端子 响应于上拉控制代码数据和下拉控制代码数据。 输出驱动器具有公共连接的上拉和下拉晶体管阵列，以及连接到输出驱动器的上拉和下拉晶体管阵列的补偿单元，以补偿上拉和下拉的量化误差 下载控制代码数据。 阻抗控制器执行比较和计数操作，使得阻抗检测器的第一和第二输出值近似为预定的参考值，并产生上拉和下拉控制代码数据。

公开(公告)号：US07385414B2

公开(公告)日：2008-06-10

申请号：US11417969

申请日：2006-05-04

申请人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

发明人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278 ,  H03K19/0005

摘要： A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

摘要翻译： 具有阻抗控制的驱动电路包括具有多个晶体管的阻抗匹配阵列单元，所述多个晶体管根据由控制代码数据产生的阵列驱动控制信号选择性地驱动;以及更新禁止控制单元，用于产生传输控制信号 在内部数据转换期间发生的第一时间间隔期间禁止驱动晶体管，并将传输控制信号施加到阻抗匹配阵列单元。

公开(公告)号：US20060250157A1

公开(公告)日：2006-11-09

申请号：US11417969

申请日：2006-05-04

申请人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

发明人： Tae-Hyoung Kim ,  Ji-Suk Kwon ,  Uk-Rae Cho

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H03K19/0005

摘要： A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

摘要翻译： 具有阻抗控制的驱动电路包括具有多个晶体管的阻抗匹配阵列单元，所述多个晶体管根据由控制代码数据产生的阵列驱动控制信号选择性地驱动;以及更新禁止控制单元，用于产生传输控制信号 在内部数据转换期间发生的第一时间间隔期间禁止驱动晶体管，并将传输控制信号施加到阻抗匹配阵列单元。

公开(公告)号：US07245158B2

公开(公告)日：2007-07-17

申请号：US11266544

申请日：2005-11-03

申请人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

发明人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

IPC分类号： G11C8/00 ,  G11C11/34

CPC分类号： G11C8/14 ,  H03K3/00 ,  H03K17/00

摘要： A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

摘要翻译： 半导体存储器件中的电路布线布置包括具有彼此串联连接的沟道的第一和第二p型MOS晶体管，以及具有与第二p型漏极并联连接的源极的第一和第二n型MOS晶体管 MOS晶体管，形成解码器NOR门控部分的p型和n型MOS晶体管。 第一和第二n型MOS晶体管分别具有连接到第一和第二主线的漏极和连接到截面线的源极。 分别施加用于第一和第二访问的选择信号的第一和第二p型MOS晶体管。 第一和第二p型MOS晶体管在第一区域中共享彼此的有源结。 第一和第二n型MOS晶体管在截面线的方向上与第一区域间隔开并且具有独立的有源结。

公开(公告)号：US20060114030A1

公开(公告)日：2006-06-01

申请号：US11266544

申请日：2005-11-03

申请人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

发明人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

IPC分类号： H03K19/00

CPC分类号： G11C8/14 ,  H03K3/00 ,  H03K17/00

摘要： A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

摘要翻译： 半导体存储器件中的电路布线布置包括具有彼此串联连接的沟道的第一和第二p型MOS晶体管，以及具有与第二p型漏极并联连接的源极的第一和第二n型MOS晶体管 MOS晶体管，形成解码器NOR门控部分的p型和n型MOS晶体管。 第一和第二n型MOS晶体管分别具有连接到第一和第二主线的漏极和连接到截面线的源极。 分别施加用于第一和第二访问的选择信号的第一和第二p型MOS晶体管。 第一和第二p型MOS晶体管在第一区域中共享彼此的有源结。 第一和第二n型MOS晶体管在截面线的方向上与第一区域间隔开并且具有独立的有源结。