公开(公告)号：US07986161B2

公开(公告)日：2011-07-26

申请号：US12327294

申请日：2008-12-03

申请人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K17/16

CPC分类号： H03K19/018585 ,  H04L25/0298

摘要： A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.

摘要翻译： 终端电阻电路包括控制信号发生器，用于产生当校准码具有预定值时其逻辑值改变的控制信号，响应于校准码分别导通/关断的多个并联电阻器，以及电阻值 改变单元，用于响应于控制信号改变终端电阻电路的总电阻值。

公开(公告)号：US07929358B2

公开(公告)日：2011-04-19

申请号：US12327397

申请日：2008-12-03

申请人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G11C7/10

CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

摘要翻译： 数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据 数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

公开(公告)号：US07952388B1

公开(公告)日：2011-05-31

申请号：US12648477

申请日：2009-12-29

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/017509 ,  H03K19/018514 ,  H03K19/018528

摘要： A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.

摘要翻译： 一种半导体器件包括：摆动电平移位单元，被配置为使用第一电源电压作为电源电压，接收围绕第一电压电平摆动的CML时钟，并将CML时钟的摆幅参考电压电平移位到第二电压电平 低于第一电压电平的CML时钟传送缓冲单元，以及CML时钟传送缓冲单元，被配置为使用第二电源电压作为电源电压，并缓冲从摆动电平移位单元传送的CML时钟，并围绕第二电压电平摆动。

公开(公告)号：US20100007375A1

公开(公告)日：2010-01-14

申请号：US12327294

申请日：2008-12-03

申请人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K17/16

CPC分类号： H03K19/018585 ,  H04L25/0298

摘要： A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.

摘要翻译： 终端电阻电路包括控制信号发生器，用于产生当校准码具有预定值时其逻辑值改变的控制信号，响应于校准码分别导通/关断的多个并联电阻器，以及电阻值 改变单元，用于响应于控制信号改变终端电阻电路的总电阻值。

公开(公告)号：US08314651B2

公开(公告)日：2012-11-20

申请号：US12647875

申请日：2009-12-28

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.

摘要翻译： 内部电压发生器包括：检测单元，被配置为与参考电压相比检测内部电压的电平; 第一驱动单元，被配置为响应于所述检测单元的输出信号，对输出所述内部电压的内部电压端子进行放电; 电流检测单元，被配置为检测流过所述第一驱动单元的放电电流; 以及第二驱动单元，其被配置为响应于所述电流检测单元的输出信号对所述内部电压端子进行充电。

公开(公告)号：US20110291759A1

公开(公告)日：2011-12-01

申请号：US12833154

申请日：2010-07-09

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03F3/45

CPC分类号： H03F3/45192

摘要： A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

摘要翻译： 轨到轨放大器包括：NMOS型放大单元，被配置为对差分输入信号的DC电平高于第一阈值的区域中的差分输入信号进行放大操作，PMOS型折叠共源共栅放大 被配置为对差分输入信号的DC电平低于高于第一阈值的第二阈值的区域中的差分输入信号进行放大操作的单元，PMOS型折叠共源共栅放大单元是 级联耦合到NMOS型放大单元，以及自适应偏置单元，被配置为在差分输入信号的DC电平高于第二阈值的区域中断PMOS型折叠共源共栅放大单元的电流路径 响应于差分输入信号。

公开(公告)号：US08130034B2

公开(公告)日：2012-03-06

申请号：US12833154

申请日：2010-07-09

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03F3/45

CPC分类号： H03F3/45192

摘要： A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

摘要翻译： 轨到轨放大器包括：NMOS型放大单元，被配置为对差分输入信号的DC电平高于第一阈值的区域中的差分输入信号进行放大操作，PMOS型折叠共源共栅放大 被配置为对差分输入信号的DC电平低于高于第一阈值的第二阈值的区域中的差分输入信号进行放大操作的单元，PMOS型折叠共源共栅放大单元是 级联耦合到NMOS型放大单元，以及自适应偏置单元，被配置为在差分输入信号的DC电平高于第二阈值的区域中断PMOS型折叠共源共栅放大单元的电流路径 响应于差分输入信号。

公开(公告)号：US20100061157A1

公开(公告)日：2010-03-11

申请号：US12327397

申请日：2008-12-03

申请人： Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G11C7/00 ,  G11C8/18 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

摘要翻译： 数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据 数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

公开(公告)号：US20100013535A1

公开(公告)日：2010-01-21

申请号：US12344642

申请日：2008-12-29

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03K3/00

CPC分类号： H03K3/356139 ,  H03K21/023

摘要： A latch circuit includes a data input/output unit configured to form a current path through a first node in response to an input data to output an output data, a holding unit configured to form a current path through a second node in response to the output data to store the output data, and a clock input unit coupled to the first and second nodes in parallel in response to a clock.

摘要翻译： 锁存电路包括：数据输入/输出单元，被配置为响应于输入数据形成通过第一节点的电流路径以输出输出数据;保持单元，被配置为响应于输出形成通过第二节点的电流路径 用于存储输出数据的数据，以及响应于时钟并行耦合到第一和第二节点的时钟输入单元。

公开(公告)号：US20130162311A1

公开(公告)日：2013-06-27

申请号：US13607234

申请日：2012-09-07

申请人： Dae-Han KWON ,  Yong-Ju Kim ,  Taek-Sang Song

发明人： Dae-Han KWON ,  Yong-Ju Kim ,  Taek-Sang Song

IPC分类号： H03L7/06 ,  H03K5/00

CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/235

摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

摘要翻译： 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为滤波输入信号并生成滤波的 信号与操作时钟同步。