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    PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF
    2.
    发明申请
    PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF 有权

    公开(公告)号：US20220028773A1

    公开(公告)日：2022-01-27

    申请号：US16934024

    申请日：2020-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Lin Lu ,  Jiun-Yi Wu ,  Kai-Chiang Wu

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L21/683

    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, an insulating encapsulation, a buffer layer, a semiconductor device and a stiffener ring is provided. The redistribution circuit structure includes a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The insulating encapsulation is disposed on the first surface of the redistribution circuit structure and laterally encapsulating the wiring substrate. The buffer layer is disposed over the second surface of the redistribution circuit structure. The semiconductor device is disposed on the buffer layer, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure. The stiffener ring is adhered with the buffer layer by an adhesive.

    Integrated fan-out package with antenna components and manufacturing method thereof
    3.
    发明授权
    Integrated fan-out package with antenna components and manufacturing method thereof 有权

    公开(公告)号：US11145595B2

    公开(公告)日：2021-10-12

    申请号：US16706805

    申请日：2019-12-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

    IPC: H01L23/52 ,  H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

    INTEGRATED FAN-OUT PACKAGE
    7.
    发明申请
    INTEGRATED FAN-OUT PACKAGE 审中-公开

    公开(公告)号：US20190067039A1

    公开(公告)日：2019-02-28

    申请号：US15690300

    申请日：2017-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

    IPC: H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.

    Package structure and manufacturing method thereof
    9.
    发明授权
    Package structure and manufacturing method thereof 有权

    公开(公告)号：US11289418B2

    公开(公告)日：2022-03-29

    申请号：US16882521

    申请日：2020-05-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Ling Hwang ,  Chun-Lin Lu ,  Kai-Chiang Wu

    IPC: H01L23/522 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/66

    Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

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