公开(公告)号：US20210097226A1

公开(公告)日：2021-04-01

申请号：US17121174

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/20 ,  H01L21/66

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US12204842B2

公开(公告)日：2025-01-21

申请号：US18359648

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/00 ,  H01L21/66 ,  G06F30/30 ,  G06F111/06 ,  G06F119/18 ,  G06F119/22

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US20220284167A1

公开(公告)日：2022-09-08

申请号：US17827529

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/20 ,  H01L21/66

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US11748551B2

公开(公告)日：2023-09-05

申请号：US17827529

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/20 ,  H01L21/66 ,  G03F7/00 ,  G06F111/06 ,  G06F30/30 ,  G06F119/18 ,  G06F119/22

CPC classification number: G06F30/398 ,  G03F7/705 ,  G03F7/7065 ,  G03F7/70433 ,  G03F7/70491 ,  G03F7/70616 ,  H01L22/12 ,  G06F30/30 ,  G06F2111/06 ,  G06F2119/18 ,  G06F2119/22

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US20200089130A1

公开(公告)日：2020-03-19

申请号：US16250128

申请日：2019-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G03F7/20 ,  G06F17/50

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US20230367951A1

公开(公告)日：2023-11-16

申请号：US18359648

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/00 ,  H01L21/66 ,  G06F111/06 ,  G06F30/30 ,  G06F119/18 ,  G06F119/22

CPC classification number: G06F30/398 ,  G03F7/70433 ,  G03F7/70491 ,  G03F7/7065 ,  H01L22/12 ,  G03F7/705 ,  G03F7/70616 ,  G06F2111/06 ,  G06F30/30 ,  G06F2119/18 ,  G06F2119/22

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

公开(公告)号：US11347926B2

公开(公告)日：2022-05-31

申请号：US17121174

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bing-Siang Chao

IPC: G06F30/398 ,  G03F7/20 ,  H01L21/66 ,  G06F111/06 ,  G06F30/30 ,  G06F119/18 ,  G06F119/22

Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.