Gate Structure and Method
    1.
    发明申请

    公开(公告)号:US20200243396A1

    公开(公告)日:2020-07-30

    申请号:US16853474

    申请日:2020-04-20

    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

    Gate Structure and Method
    2.
    发明申请

    公开(公告)号:US20190333822A1

    公开(公告)日:2019-10-31

    申请号:US15964177

    申请日:2018-04-27

    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

    Gate Structure and Method
    4.
    发明申请

    公开(公告)号:US20210272852A1

    公开(公告)日:2021-09-02

    申请号:US17246998

    申请日:2021-05-03

    Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.

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