公开(公告)号：US20150234979A1

公开(公告)日：2015-08-20

申请号：US14705021

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

公开(公告)号：US20130167095A1

公开(公告)日：2013-06-27

申请号：US13770158

申请日：2013-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

公开(公告)号：US20150154343A1

公开(公告)日：2015-06-04

申请号：US14562793

申请日：2014-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang YEH ,  Cheng-Hung YEH ,  Chi-Ting HUANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036

Abstract: A method for timing analysis includes using the processor to determine an impedance profile of a coupling between at least a first inter-level via (ILV) and a a second ILV or a device, as a function of at least different frequency values. The impedance profile includes a plurality of impedance values corresponding to respective frequency values. An effective capacitance value corresponding to each respective impedance value is determined. At least one table is provided with respective impedance values and respective effective capacitance values for each respective frequency value. An RC extraction of a design layout of an ILV circuit is conducted using the populated table and based on determined effective capacitance values.

Abstract translation: 一种用于定时分析的方法包括使用该处理器来确定至少第一级间通路（ILV）和第二ILV或器件之间的耦合的阻抗曲线，作为至少不同频率值的函数。 阻抗曲线包括对应于各个频率值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 为每个相应的频率值提供至少一个表，其具有相应的阻抗值和相应的有效电容值。 使用填充表并基于确定的有效电容值来进行ILV电路的设计布局的RC提取。