公开(公告)号：US20150193568A1

公开(公告)日：2015-07-09

申请号：US14663476

申请日：2015-03-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ashok MEHTA

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5022 ,  G06F2217/86

Abstract: A method of transmitting data is disclosed. At least one system block of a system-on-chip (SoC) is modeled at an untimed functional level in first and second untimed functional models. First and second transaction level (TL) models of the at least one system block system block are modeled at a transaction level (TL) using the first and second untimed functional models, respectively. First and second cycle accurate (CA) models are modeled at a cycle accurate (CA) level using the first and second TL models, respectively. Data is transmitted from the first untimed functional model to the first CA model, from the first CA model to the second CA model via a CA bus, and from the second CA model to the second untimed functional model.

Abstract translation: 公开了发送数据的方法。 系统级芯片（SoC）的至少一个系统块在第一和第二未定义功能模型中的未定义功能级别被建模。 至少一个系统块系统块的第一和第二事务级（TL）模型分别使用第一和第二未定义的功能模型在事务级（TL）建模。 第一和第二周期精确（CA）模型分别使用第一和第二TL模型在循环准确（CA）级别建模。 数据从第一个未定义的功能模型传输到第一个CA模型，从第一个CA模型到第二个CA模型，经由CA总线，从第二个CA模型传输到第二个未定义的功能模型。

公开(公告)号：US20150234979A1

公开(公告)日：2015-08-20

申请号：US14705021

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

公开(公告)号：US20150123699A1

公开(公告)日：2015-05-07

申请号：US14595251

申请日：2015-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Stanley JOHN ,  Ashok MEHTA ,  Sandeep Kumar GOEL ,  Kai-Yuan TING

IPC: G01R31/28

CPC classification number: G01R31/2886 ,  G01R31/318513

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract translation: 公开了一种用于多芯片3D IC的功能验证的系统和方法。 该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。 该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

公开(公告)号：US20130167095A1

公开(公告)日：2013-06-27

申请号：US13770158

申请日：2013-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

公开(公告)号：US20130074019A1

公开(公告)日：2013-03-21

申请号：US13676259

申请日：2012-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ashok MEHTA

IPC: G06F17/50

CPC classification number: G01R31/318357

Abstract: A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level, respectively. A stimulus transaction is generated at a first testbench at the first level. The stimulus transaction is transmitted from the first testbench to a second testbench at the second level. The stimulus transaction is transformed into a first response transaction, using the first model, at the first level. The stimulus transaction received at the second testbench is transformed into a second response transaction, using the second model, at the second level. Functionality of the SoC at the first and second levels is verified based on the first and second response transactions.

Abstract translation: 一种用于验证片上系统（SoC）的功能的方法包括分别在第一级别和第二级别上对第一和第二模型中的系统块进行建模，第一级别和第二级别低于第一级别。 在第一级的第一测试台产生刺激事务。 刺激事务从第一个测试台传输到第二个测试台。 在第一级，刺激交易被转换为使用第一模型的第一响应交易。 在第二个测试台处接收到的刺激事务在第二个级别被转换成第二个响应事务，使用第二个模型。 基于第一和第二响应事务验证第一和第二级的SoC的功能。