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    SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
    1.
    发明申请
    SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS 有权

    公开(公告)号：US20230113905A1

    公开(公告)日：2023-04-13

    申请号：US18080680

    申请日：2022-12-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Yun-Han LEE ,  Saman M.I. ADHAM ,  Marat GERSHOIG

    IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/317

    Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

    CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES
    3.
    发明申请
    CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES 有权
    诊断扫描链失败的电路和方法

    公开(公告)号：US20160041225A1

    公开(公告)日：2016-02-11

    申请号：US14920718

    申请日：2015-10-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL

    IPC: G01R31/3177

    CPC classification number: G01R31/318541 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318561

    Abstract: A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

    Abstract translation: 电路包括以环形网络拓扑布置的多个扫描链。 每个扫描链包括多个扫描块，所述多个扫描块中的每一个包括存储元件和切换装置。 每个开关装置包括第一输入，其被配置为接收来自与其中设置有开关装置的扫描链不同的扫描链中的存储元件的输出，以及第二输入，被配置为接收功能逻辑信号或测试扫描之一 信号。 所述切换装置被配置为选择性地将所述第一输入或所述第二输入耦合到所述存储元件的输入。

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    4.
    发明申请
    PHASE-LOCKED LOOP MONITOR CIRCUIT 有权

    公开(公告)号：US20210281268A1

    公开(公告)日：2021-09-09

    申请号：US17330818

    申请日：2021-05-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

    IPC: H03L7/23 ,  H03L7/091 ,  H03L7/095

    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    5.
    发明申请
    PHASE-LOCKED LOOP MONITOR CIRCUIT 审中-公开

    公开(公告)号：US20200304133A1

    公开(公告)日：2020-09-24

    申请号：US16894607

    申请日：2020-06-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

    IPC: H03L7/23 ,  H03L7/091 ,  H03L7/095

    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

    POWER ESTIMATION
    6.
    发明申请
    POWER ESTIMATION 审中-公开

    公开(公告)号：US20190332161A1

    公开(公告)日：2019-10-31

    申请号：US16505347

    申请日：2019-07-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kai-Yuan TING ,  Shereef SHEHATA ,  Tze-Chiang HUANG ,  Sandeep Kumar GOEL ,  Mei WONG ,  Yun-Han LEE

    IPC: G06F1/3228 ,  G06F1/28

    Abstract: A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a pre-determined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.

    SYSTEM AND METHOD FOR SYSTEM-LEVEL PARAMETER ESTIMATION
    7.
    发明申请
    SYSTEM AND METHOD FOR SYSTEM-LEVEL PARAMETER ESTIMATION 审中-公开
    系统和方法用于系统级参数估计

    公开(公告)号：US20170076029A1

    公开(公告)日：2017-03-16

    申请号：US15260143

    申请日：2016-09-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tze-Chiang HUANG ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Yun-Han LEE ,  Shereef SHEHATA ,  Mei WONG

    IPC: G06F17/50 ,  G06Q50/18

    Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.

    Abstract translation: 公开了一种包括提供IP银行，应用银行和技术银行的方法; 基于IP银行和应用银行生成分层表; 通过使用技术组对与分层表相对应的性能值，功率值，面积值和成本值中的至少一个进行估计，输出作为系统的制造基础的结果数据 。

    METHOD AND SYSTEM FOR FUNCTIONAL SAFETY VERIFICATION
    9.
    发明申请
    METHOD AND SYSTEM FOR FUNCTIONAL SAFETY VERIFICATION 审中-公开

    公开(公告)号：US20180149698A1

    公开(公告)日：2018-05-31

    申请号：US15592602

    申请日：2017-05-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Sandeep Kumar GOEL ,  Abhishek KONERU ,  Tri NGO ,  Yun-Han LEE

    IPC: G01R31/3185 ,  G01R31/3181 ,  G01R31/3177

    CPC classification number: G01R31/3177 ,  G06F17/5045

    Abstract: A system includes a memory and a processor. The processor is configured to execute computer program codes to perform operations below. A netlist of a functional unit is transformed to a first matrix. The netlist includes information associated with nodes and flip-flops. A first node is selected from the nodes according to the first matrix and a second matrix, to generate a fault list. The second matrix includes weighting values for the nodes. The first node is determined to be associated with a maximum number of the flip-flops. A fault injection is performed on the functional unit. The functional unit is analyzed according to the netlist and the fault list, to generate a first file. A safety mechanism unit is analyzed to generate a second file. A failure is detected according to the first file or a combination of the first file and the second file.

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