公开(公告)号：US20180152193A1

公开(公告)日：2018-05-31

申请号：US15711201

申请日：2017-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

IPC: H03L7/23 ,  H03L7/095 ,  H03L7/091

CPC classification number: H03L7/23 ,  H03K19/21 ,  H03L7/091 ,  H03L7/095

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

公开(公告)号：US20210281268A1

公开(公告)日：2021-09-09

申请号：US17330818

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

IPC: H03L7/23 ,  H03L7/091 ,  H03L7/095

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

公开(公告)号：US20200304133A1

公开(公告)日：2020-09-24

申请号：US16894607

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

IPC: H03L7/23 ,  H03L7/091 ,  H03L7/095

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

公开(公告)号：US20180164369A1

公开(公告)日：2018-06-14

申请号：US15602365

申请日：2017-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sandeep Kumar GOEL ,  Stanley JOHN ,  Ji-Jan CHEN ,  Yun-Han LEE

IPC: G01R31/3183 ,  H03K19/20 ,  G01R31/28

CPC classification number: G01R31/3183 ,  G01R31/2834 ,  H03K19/20

Abstract: A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.

公开(公告)号：US20150234979A1

公开(公告)日：2015-08-20

申请号：US14705021

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。

公开(公告)号：US20150123699A1

公开(公告)日：2015-05-07

申请号：US14595251

申请日：2015-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Stanley JOHN ,  Ashok MEHTA ,  Sandeep Kumar GOEL ,  Kai-Yuan TING

IPC: G01R31/28

CPC classification number: G01R31/2886 ,  G01R31/318513

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract translation: 公开了一种用于多芯片3D IC的功能验证的系统和方法。 该系统和方法包括可复用的验证环境，用于单独地对一堆模具中的每个模具进行测试，而不必同时操作堆叠中的所有模具。 该系统和方法包括将来自芯片验证测试的输入/输出（“IO”）跟踪从第一格式转换为第二格式以提高性能。

公开(公告)号：US20130167095A1

公开(公告)日：2013-06-27

申请号：US13770158

申请日：2013-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ashok MEHTA ,  Stanley JOHN ,  Kai-Yuan TING ,  Sandeep Kumar GOEL ,  Chao-Yang YEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

Abstract translation: 一种系统包括被配置为产生集成电路（IC）裸片的布局的由处理器实现的工具。 至少一个非暂时机器可读存储介质包括分别由第一和第二集成电路（IC）管芯上形成的第一和第二电路图案的第一栅极级描述编码的第一部分，以及用第 从处理器实现的工具接收的第一和第二电路图案的第二门级描述。 第二门级描述包括电源和接地端口，并且第一门级描述不包括电源和接地端口。 提供了一种处理器实现的第一验证模块，用于比较第一和第二门级描述并输出第一和第二电路图案的经验证的第二门级描述。