公开(公告)号：US09551923B2

公开(公告)日：2017-01-24

申请号：US14247409

申请日：2014-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Sen Wang ,  Ming-Yi Lin ,  Chen-Hung Lu ,  Jyh-Kang Ting

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

Abstract translation: 一些实施例涉及设计集成电路布局的方法。 在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。 连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。 产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。 第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。

公开(公告)号：US09405879B2

公开(公告)日：2016-08-02

申请号：US14231858

申请日：2014-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Sen Wang ,  Ting Yu Chen ,  Ken-Hsien Hsieh ,  Ming-Yi Lin ,  Chen-Hung Lu

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5081 ,  G06F9/455 ,  G06F17/5068 ,  G06F17/5072

Abstract: Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.

Abstract translation: 一些实施例涉及分层布局设计的方法，包括根据规定IC内的相邻布局特征之间的最小设计规则距离的设计规则来形成集成电路（IC）的布局。 形成布局包括分别形成具有第一和第二布局特征的第一和第二标准单元，使得第一和第二布局特征之间的距离小于最小设计规则距离。 该方法还包括配置设计规则检查（DRC）以忽略该失败。 相反，通过合并第一和第二布局特征，或者通过移除第一或第二布局特征的一部分来增加第一和第二布局特征之间的距离来大于或等于 最小距离。

公开(公告)号：US20150286765A1

公开(公告)日：2015-10-08

申请号：US14247409

申请日：2014-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Sen Wang ,  Ming-Yi Lin ,  Chen-Hung Lu ,  Jyh-Kang Ting

IPC: G06F17/50

CPC classification number: G03F1/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

Abstract translation: 一些实施例涉及设计集成电路布局的方法。 在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。 连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。 产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。 第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。