公开(公告)号：US20150050810A1

公开(公告)日：2015-02-19

申请号：US13967477

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Liang-Yao Lee ,  Jyh-Kang Ting ,  Tsung-Chieh Tsai ,  Juing-Yu Wu

IPC: H01L21/308

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/70283

Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner. Accordingly, the second distance generally prevents the rounded corner of the exposure region from overlapping the active device region.

Abstract translation: 提供了一种用于在光刻工艺中改善拐角圆角效果的方法。 提供具有有源器件区域的半导体工件，并且在半导体工件上形成光致抗蚀剂层。 提供掩模用于图案化光致抗蚀剂层，其中掩模包括具有与有源器件区域相关联的尖角的图案。 尖角与有源器件区分离第一方向第一距离和第二方向上的第二距离，其中第一距离满足光刻工艺的最小标准，并且其中第二距离大于第一距离 距离。 然后将光致抗蚀剂层暴露于辐射源，并且辐射源通过掩模对光致抗蚀剂层进行图案，在半导体工件上限定具有与锐角相关的圆角的曝光区域。 因此，第二距离通常防止曝光区域的圆角与有源器件区域重叠。

公开(公告)号：US08806417B1

公开(公告)日：2014-08-12

申请号：US13871165

申请日：2013-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chao ,  Jyh-Kang Ting ,  Chin-An Chen ,  Pei-tzu Wu ,  Chun-Yi Lee

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A target integrated circuit layout having a plurality of design rules having minimum rules and standard rules used in the target integrated circuit layout is provided. First and second design rule checks are performed, where respective first and second sets of violations of the plurality of design rules and each design rule associated with the first and second sets of violations are recorded. An analysis is performed on the first and second sets of violations, each design rule associated with the first and second sets of violations, and a frequency of usage of each of the plurality of design rules, and a rule usage rate is determined having a number of minimum rules used overall and a number of overall violations of the design rules. An interactive rule database is formed having statistics associated with the rule usage rate for subsequent implementation in an integrated circuit.

Abstract translation: 提供了具有在目标集成电路布局中使用的具有最小规则和标准规则的多个设计规则的目标集成电路布局。 执行第一和第二设计规则检查，其中记录了与第一组和第二组违反相关联的多个设计规则和每个设计规则的相应的第一和第二组违反。 对第一和​​第二组违规进行分析，每个设计规则与第一和第二组违规相关联，以及多个设计规则中的每一个的使用频率，并且确定规则使用率具有数字 整体使用的最低规则和一些违反设计规则的违规行为。 形成具有与规则使用率相关联的统计数据的交互式规则数据库，用于集成电路中的后续实现。

公开(公告)号：US09551923B2

公开(公告)日：2017-01-24

申请号：US14247409

申请日：2014-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Sen Wang ,  Ming-Yi Lin ,  Chen-Hung Lu ,  Jyh-Kang Ting

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

Abstract translation: 一些实施例涉及设计集成电路布局的方法。 在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。 连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。 产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。 第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。

公开(公告)号：US09746783B2

公开(公告)日：2017-08-29

申请号：US13967477

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Liang-Yao Lee ,  Jyh-Kang Ting ,  Tsung-Chieh Tsai ,  Juing-Yi Wu

IPC: H01L21/308 ,  G03F7/20 ,  G03F1/36

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F7/70283

Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner. Accordingly, the second distance generally prevents the rounded corner of the exposure region from overlapping the active device region.

公开(公告)号：US20150286765A1

公开(公告)日：2015-10-08

申请号：US14247409

申请日：2014-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Sen Wang ,  Ming-Yi Lin ,  Chen-Hung Lu ,  Jyh-Kang Ting

IPC: G06F17/50

CPC classification number: G03F1/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

Abstract translation: 一些实施例涉及设计集成电路布局的方法。 在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。 连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。 产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。 第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。

公开(公告)号：US09047437B2

公开(公告)日：2015-06-02

申请号：US14289256

申请日：2014-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-An Chen ,  Pei-Tzu Wu ,  Tsung-Chieh Tsai ,  Juing-Yi Wu ,  Jyh-Kang Ting

IPC: G06F15/04 ,  G06F17/50

CPC classification number: G06F17/5081

Abstract: Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.

Abstract translation: 提供了一种用于设计集成电路或其他半导体器件的布局的系统和方法，同时通过与显示设计布局的GUI对接地直接访问设计规则和设计特征库。 设计规则可以直接链接到图案库的设计特征并导入设备布局。 设计规则可以在设计布局时进行直接访问，或者在进行设计规则检查时，可以使用图案库中的设计特征来创建布局。