PHASE LOCKED LOOP
    1.
    发明申请
    PHASE LOCKED LOOP 审中-公开

    公开(公告)号:US20200127668A1

    公开(公告)日:2020-04-23

    申请号:US16723205

    申请日:2019-12-20

    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

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