公开(公告)号：US20250151317A1

公开(公告)日：2025-05-08

申请号：US19015324

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Chi-Hao Chang ,  Jr-Hung Li

IPC: H10D30/62 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

公开(公告)号：US20230282750A1

公开(公告)日：2023-09-07

申请号：US17841493

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang ,  Hao-Yu Chang ,  Pei-Yu Chou

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.

公开(公告)号：US20230033289A1

公开(公告)日：2023-02-02

申请号：US17668143

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

公开(公告)号：US12237419B2

公开(公告)日：2025-02-25

申请号：US17668143

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.