公开(公告)号：US12096609B2

公开(公告)日：2024-09-17

申请号：US17826754

申请日：2022-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang

IPC分类号： H10B10/00 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B10/12 ,  H01L21/0332 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/18

摘要： The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length.

公开(公告)号：US20240222427A1

公开(公告)日：2024-07-04

申请号：US18442794

申请日：2024-02-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC分类号： H01L29/06 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H10B10/00

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H10B10/12

摘要： In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US12009429B2

公开(公告)日：2024-06-11

申请号：US17872825

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/823443 ,  H01L21/823821 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/66795

摘要： In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

公开(公告)号：US20230268225A1

公开(公告)日：2023-08-24

申请号：US17651615

申请日：2022-02-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Yi-Nien Su ,  Huang-Ming Chen

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L23/532

CPC分类号： H01L21/76835 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/02274 ,  H01L21/02203 ,  H01L21/02126 ,  H01L21/02112 ,  H01L29/66795 ,  H01L23/53295 ,  H01L21/76802 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02214

摘要： A method for manufacturing a semiconductor device includes forming a source/drain region on a semiconductor fin. The source/drain region is adjacent to a dummy gate. The method further includes forming a first dielectric layer over the source/drain region and the dummy gate. The first dielectric layer has a dielectric constant of 3.5 or less. The first dielectric layer may include boron nitride or silicon dioxide with Si-CH3 bonds.

公开(公告)号：US11515165B2

公开(公告)日：2022-11-29

申请号：US16898655

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC分类号： H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

摘要： In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

公开(公告)号：US20220359650A1

公开(公告)日：2022-11-10

申请号：US17874732

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC分类号： H01L29/06 ,  H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/764 ,  H01L29/417

摘要： In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

公开(公告)号：US11355637B2

公开(公告)日：2022-06-07

申请号：US16917306

申请日：2020-06-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Feng Fu ,  Guan-Ren Wang ,  Yun-Min Chang ,  Yu-Lien Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

公开(公告)号：US11302577B2

公开(公告)日：2022-04-12

申请号：US16746544

申请日：2020-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/308

摘要： A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.

公开(公告)号：US20210296497A1

公开(公告)日：2021-09-23

申请号：US17339054

申请日：2021-06-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Peng Wang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768

摘要： The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.

公开(公告)号：US10692720B2

公开(公告)日：2020-06-23

申请号：US16679617

申请日：2019-11-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lien Huang ,  Tsai-Chun Li ,  Huan-Just Lin ,  Huang-Ming Chen ,  Yang-Cheng Wu ,  Cheng-Hua Yang

IPC分类号： H01L21/033 ,  G03F7/36 ,  G03F7/20 ,  H01J37/32 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L21/67

摘要： Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.