公开(公告)号：US12272554B2

公开(公告)日：2025-04-08

申请号：US18227231

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin Wei ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  G03F1/22 ,  G03F7/00 ,  H01L21/308

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US20250112102A1

公开(公告)日：2025-04-03

申请号：US18980281

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Jen Sung ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/10

Abstract: A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

公开(公告)号：US11894435B2

公开(公告)日：2024-02-06

申请号：US17193626

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/76832 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/401 ,  H01L29/7851

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

公开(公告)号：US11843028B2

公开(公告)日：2023-12-12

申请号：US17322087

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Fu-Kai Yang ,  Chen-Ming B. Lee ,  Mei-Yun Wang ,  Jr-Hung Li ,  Bo-Cyuan Lu

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L21/32

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/7855 ,  H01L21/32 ,  H01L21/823437

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

公开(公告)号：US11784046B2

公开(公告)日：2023-10-10

申请号：US17150356

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin Wei ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  H01L21/308 ,  G03F7/20 ,  G03F1/22 ,  G03F7/00

CPC classification number: H01L21/0332 ,  G03F1/22 ,  G03F7/70033 ,  H01L21/0334 ,  H01L21/3081

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US11444173B2

公开(公告)日：2022-09-13

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Jin-Mu Yin ,  Tsung-Chieh Hsiao ,  Chia-Lin Chuang ,  Li-Zhen Yu ,  Dian-Hau Chen ,  Shih-Wei Wang ,  De-Wei Yu ,  Chien-Hao Chen ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun-Cheng Chou ,  Ying-Liang Chuang ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Cheng-Po Chau ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/45 ,  H01L29/08 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US11271083B2

公开(公告)日：2022-03-08

申请号：US16805862

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Jr-Hung Li ,  Tai-Chun Huang ,  Tze-Liang Lee ,  Chung-Ting Ko ,  Jr-Yu Chen ,  Wan-Chen Hsieh

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

公开(公告)号：US20210098365A1

公开(公告)日：2021-04-01

申请号：US16805834

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC: H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US12237419B2

公开(公告)日：2025-02-25

申请号：US17668143

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

公开(公告)号：US20230317469A1

公开(公告)日：2023-10-05

申请号：US17711885

申请日：2022-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Po-Hsien Cheng ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L29/66795 ,  H01L29/6653 ,  H01L29/456 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.