公开(公告)号：US12106033B2

公开(公告)日：2024-10-01

申请号：US18341545

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko ,  Chi-Lin Liu ,  Hui-Zhong Zhuang

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  H01L23/52 ,  H01L23/522

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  H01L23/52 ,  H01L23/5222

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

公开(公告)号：US11437321B2

公开(公告)日：2022-09-06

申请号：US16846690

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66 ,  H01L27/118

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.

公开(公告)号：US20180350743A1

公开(公告)日：2018-12-06

申请号：US16057875

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L29/66 ,  H01L27/02 ,  H01L21/768 ,  H01L27/088 ,  H01L23/535 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L23/5286 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/66545

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

公开(公告)号：US12300699B2

公开(公告)日：2025-05-13

申请号：US17875257

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei Wu ,  Chi-Yu Lu ,  Ting-Yu Chen ,  Li-Chun Tien

IPC: H01L27/118 ,  H01L27/02

Abstract: A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.

公开(公告)号：US20240086611A1

公开(公告)日：2024-03-14

申请号：US18514356

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Hsuan Chiu ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Kuang-Ching Chang

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

公开(公告)号：US11868697B2

公开(公告)日：2024-01-09

申请号：US17459485

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Hsuan Chiu ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Kuang-Ching Chang

IPC: G06F30/00 ,  G06F30/392

CPC classification number: G06F30/392

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

公开(公告)号：US20230068097A1

公开(公告)日：2023-03-02

申请号：US17459485

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Hsuan CIOU ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Kuang-Ching Chang

IPC: G06F30/392

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

公开(公告)号：US10672708B2

公开(公告)日：2020-06-02

申请号：US15170246

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/485 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/118

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.

公开(公告)号：US20170154848A1

公开(公告)日：2017-06-01

申请号：US15170246

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L23/535 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.

公开(公告)号：US11734481B2

公开(公告)日：2023-08-22

申请号：US17321574

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chi-Yu Lu ,  Yi-Hsin Ko

IPC: G06F30/327 ,  H01L23/52 ,  H01L23/522 ,  G06F30/392 ,  G06F30/398

CPC classification number: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/52 ,  H01L23/5222

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.