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公开(公告)号：US11239228B2
公开(公告)日：2022-02-01
申请号：US16921894
申请日：2020-07-06
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC分类号： G06F7/50 , H01L27/02 , H01L27/088 , H01L27/092 , G06F30/392 , H01L27/118 , G06F111/20 , G06F119/18
摘要： An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
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公开(公告)号：US11217553B2
公开(公告)日：2022-01-04
申请号：US16587539
申请日：2019-09-30
发明人： Hsiang-Jen Tseng , Wei-Yu Chen , Ting-Wei Chiang , Li-Chun Tien
IPC分类号： H01L23/00 , H01L25/065 , H01L23/528 , H01L25/00 , H01L21/768 , H01L23/48 , H01L21/822 , H01L27/06 , H01L23/535 , H01L21/74 , H01L25/07 , H01L27/118 , H01L23/522 , H01L23/532
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having a first pair of sidewalls extending in a first direction and a second pair of sidewalls. One or more of the second pair of sidewalls extend past the first pair of sidewalls in a second direction that intersects the first direction as viewed from a top-view of the semiconductor substrate. The first pair of sidewalls and the second pair of sidewalls define one or more trenches within the semiconductor substrate. An interconnecting structure including a conductive material is disposed within the one or more trenches in the semiconductor substrate. The interconnecting structure continuously extends completely through the semiconductor substrate.
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公开(公告)号：US10559558B2
公开(公告)日：2020-02-11
申请号：US15966507
申请日：2018-04-30
发明人： Fong-yuan Chang , Sheng-Hsiung Chen , Ting-Wei Chiang , Chung-Te Lin , Jung-Chan Yang , Lee-Chung Lu , Po-Hsiang Huang , Chun-Chen Chen
IPC分类号： H01L27/02 , G06F17/50 , H01L27/118
摘要： The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a wire cut between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the wire cut separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
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公开(公告)号：US10269784B2
公开(公告)日：2019-04-23
申请号：US15201200
申请日：2016-07-01
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC分类号： H01L27/02 , G06F17/50 , H01L27/088 , H01L27/092 , H01L27/118
摘要： An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
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公开(公告)号：US20170317666A1
公开(公告)日：2017-11-02
申请号：US15496575
申请日：2017-04-25
发明人： Chi-Lin Liu , Ting-Wei Chiang , Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Lee-Chung Lu , Shang-Chih Hsieh , Che Min Huang
IPC分类号： H03K3/3562 , H01L27/092 , G01R31/3177
CPC分类号： H03K3/35625 , G01R31/318541 , H01L27/092
摘要： In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.
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公开(公告)号：US09443758B2
公开(公告)日：2016-09-13
申请号：US14102548
申请日：2013-12-11
发明人： Hsiang-Jen Tseng , Wei-Yu Chen , Ting-Wei Chiang , Li-Chun Tien
IPC分类号： H01L23/00 , H01L21/768 , H01L25/065 , H01L23/528 , H01L25/00 , H01L23/48 , H01L21/822 , H01L27/06 , H01L23/535 , H01L21/74 , H01L23/522 , H01L23/532
CPC分类号： H01L24/25 , H01L21/743 , H01L21/76838 , H01L21/8221 , H01L23/481 , H01L23/522 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/535 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2225/06527 , H01L2225/06548 , H01L2924/00014 , H01L2924/13091 , H01L2924/207 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2224/85399 , H01L2224/05599
摘要： A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a substrate of a tier. Layers of the horizontal connecting structure have different patterns as viewed from above the substrate.
摘要翻译： 堆叠集成电路包括垂直连接在一起的多层。 在层的衬底内制造多层水平连接结构。 水平连接结构的层从衬底上方观察到不同的图案。
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公开(公告)号：US12056432B2
公开(公告)日：2024-08-06
申请号：US18300142
申请日：2023-04-13
发明人： Fong-yuan Chang , Chun-Chen Chen , Sheng-Hsiung Chen , Ting-Wei Chiang , Chung-Te Lin , Jung-Chan Yang , Lee-Chung Lu , Po-Hsiang Huang
IPC分类号： G06F30/30 , G06F30/392 , G06F30/394 , G06F30/398 , H01L27/02 , H01L27/118
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , H01L27/0207 , H01L27/11807 , H01L2027/11875
摘要： The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
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公开(公告)号：US11437321B2
公开(公告)日：2022-09-06
申请号：US16846690
申请日：2020-04-13
发明人： Ni-Wan Fan , Ting-Wei Chiang , Cheng-I Huang , Jung-Chan Yang , Hsiang-Jen Tseng , Lipen Yuan , Chi-Yu Lu
IPC分类号： H01L23/528 , H01L27/02 , H01L27/088 , H01L23/485 , H01L21/8234 , H01L21/768 , H01L23/535 , H01L29/66 , H01L27/118
摘要： The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.
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公开(公告)号：US11309311B2
公开(公告)日：2022-04-19
申请号：US16787964
申请日：2020-02-11
发明人： Po-Chia Lai , Shang-Wei Fang , Meng-Hung Shen , Jiann-Tyng Tzeng , Ting-Wei Chiang , Jung-Chan Yang , Stefan Rusu
IPC分类号： H01L21/44 , H01L29/40 , H01L27/07 , H01L27/02 , H01L23/485 , G06F30/392 , H01L23/64 , G06F30/394
摘要： An integrated circuit is disclosed, including a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction, at least one first conductive segment disposed in a second layer different from the first layer, and at least one via disposed between the first layer and the second layer. The at least one via is coupled between the at least one first conductive segment and one or both of the first conductive pattern and the second conductive pattern, at an output node of the integrated circuit. The at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width. The first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.
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公开(公告)号：US20200328148A1
公开(公告)日：2020-10-15
申请号：US16913697
申请日：2020-06-26
发明人： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Li-Chun Tien , Pin-Dai Sue
IPC分类号： H01L23/522 , H01L27/118 , H01L27/02
摘要： A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.
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