公开(公告)号：US20190181149A1

公开(公告)日：2019-06-13

申请号：US16278208

申请日：2019-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Wei SU ,  Yung-Lung HSU ,  Chih-Hsun LIN ,  Kun-Tsang CHUANG ,  Chiang-Ming CHUANG ,  Chia-Yi TSENG

IPC: H01L27/11521 ,  H01L27/11548 ,  H01L23/29 ,  H01L23/31 ,  H01L29/49 ,  H01L29/423 ,  H01L27/11526 ,  H01L29/788 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.

公开(公告)号：US20220359395A1

公开(公告)日：2022-11-10

申请号：US17873921

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hsung HO ,  Chia-Yi TSENG ,  Chih-Hsun LIN ,  Kun-Tsang CHUANG ,  Yung-Lung HSU

IPC: H01L23/528 ,  H01L23/544 ,  H01L29/40 ,  H01L21/66 ,  H01L23/522

Abstract: A method includes following steps. An image of a wafer is captured. A first contact region in the captured image at which the first conductive contact is rendered is identified. A second contact region in the captured image at which the second conductive contact is rendered is identified. The second conductive contact is determined as not shorted to the first conductive contact, in response to the identified second contact region in the captured image is darker than the identified first contact region in the captured image.

公开(公告)号：US20180261609A1

公开(公告)日：2018-09-13

申请号：US15456820

申请日：2017-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Wei SU ,  Yung-Lung HSU ,  Chih-Hsun LIN ,  Kun-Tsang CHUANG ,  Chiang-Ming CHUANG ,  Chia-Yi TSENG

IPC: H01L27/11521 ,  H01L29/49 ,  H01L29/788 ,  H01L23/31 ,  H01L23/29 ,  H01L27/11526 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.

公开(公告)号：US20250022940A1

公开(公告)日：2025-01-16

申请号：US18350429

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Chun LU ,  Yi-Hsing CHU ,  Chia-Yi TSENG

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure describes forming a semiconductor structure having an isolation layer surrounding a portion of a gate structure. The semiconductor structure includes a channel structure on a substrate, a first isolation layer on the substrate and surrounding the channel structure, and a gate structure on the channel structure and the first isolation layer. The gate structure includes a first portion having a first width and a second portion having a second width less than the first width. The semiconductor structure further includes a second isolation layer on the first isolation layer and surrounding the first portion of the gate structure.

公开(公告)号：US20240429285A1

公开(公告)日：2024-12-26

申请号：US18339549

申请日：2023-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Chun LU ,  Yi-Hsing CHU ,  Chia-Yi TSENG

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes forming a semiconductor structure having an isolation layer surrounding a sloped portion of a channel structure. The semiconductor structure includes a channel structure having first, second, and third portions on a substrate. The first portion has a first width. The second portion has a second width less than the first width. The third portion has a third width less than the second width. The semiconductor structure further includes a first isolation layer on the substrate and surrounding the first portion, a second isolation layer on the first isolation layer and surrounding the second portion of the channel structure, and a gate structure on the second isolation layer and surrounding the third portion of the channel structure.

公开(公告)号：US20210043566A1

公开(公告)日：2021-02-11

申请号：US17078523

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hsung HO ,  Chia-Yi TSENG ,  Chih-Hsun LIN ,  Kun-Tsang CHUANG ,  Yung-Lung HSU

IPC: H01L23/528 ,  H01L23/544 ,  H01L29/40 ,  H01L21/66 ,  H01L23/522

Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.

公开(公告)号：US20180151459A1

公开(公告)日：2018-05-31

申请号：US15588585

申请日：2017-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Hsung HO ,  Chia-Yi TSENG ,  Chih-Hsun LIN ,  Kun-Tsang CHUANG ,  Yung-Lung HSU

IPC: H01L21/66 ,  H01L21/768

CPC classification number: H01L22/32 ,  H01L21/76807 ,  H01L22/14

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.